Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
RESET S3F80P5_UM_ REV1.00
Normal Operating Mode (LVD on)
V
DD
V
LVD
t
WAIT
(4096x16x1/fosc)
V
POR
POR Reset Release
Internal Reset
Release
LVD Reset
Release
Stop Mode (LVD off)
POR detected
Reset pulse generated,
Oscillation starts
Reset Low
If "Vreset > VIH", the operating status is in STOP mode, LVD circuit is disabled in the S3F80P5X.
Figure 8-5. Reset Timing Diagram for the S3F80P5 in STOP Mode by IPOR
EXTERNAL INTERRUPT RESET
When RESET Control Bit (smart option @ 03FH) is set to ‘0’ and chip is in stop mode, if external interrupt is
occurred by among the enabled external interrupt sources, from INT0 to INT5, reset signal is generated.
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