Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
S3F80P5_UM_ REV1.00 RESET
INTERNAL POWER-ON RESET
The power-on reset circuit is built on the S3F80P5 product. When power is initially applied to the MCU, or when
V
DD
drops below the V
POR
, the POR circuit holds the MCU in reset until V
DD
has risen above the V
LVD
level.
Normal Operating Mode
V
DD
V
LVD
t
WAIT
V
POR
Internal
RESET
Release
Reset
Pulse
Figure 8-4. Timing Diagram for Internal Power-On Reset Circuit
8-5