Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
S3F80P5_UM_ REV1.00 RESET
P0&P2.0
(INT0~INT5)
Noise
Filter
External Interrupt
Control Block
P0& P2.0
Enabled
INT0~INT5
SED&R
Circuit
P0
STOP
STOPCON
Back-up
Mode
Falling Edge
Detector
Enable/
Disable
STOP
STOPCON
LVD
IPOR
Rising Edge
Detector
fosc
BT
(WDT)
Falling Edge
RESE
T
RESET Contorl Bit'1'
RESET Contorl Bit'1'
STOP
STOPCON
*RESET Control Bit: smart option bit[0] @03FH
Figure 8-2. RESET Block Diagram of the S3F80P5
8-3