Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
RESET S3F80P5_UM_ REV1.00
Watchdog Timer
STOP
(EI)external interrupt enable
P0&P2.0
(INT0-INT5)
STOP
LVD
IPOR
P0
RESET
1
2
3
4
5
RESET Contorl Bit '1'
STOP
RESET Contorl Bit '1'
*RESET Control Bit : smart option bit[0]@03FH
Figure 8-1. RESET Sources of the S3F80P5
1. The rising edge detection of LVD circuit while rising of VDD passes the level of V .
LVD
2. When POR circuit detects VDD below V , reset is generated by internal power-on reset.
POR
3. Basic Timer over-flow for watchdog timer. See the chapter 10. Basic Timer and Timer 0 for more
understanding.
4. When RESET Control Bit (smart option @ 03FH) is set to ‘0’ and chip is in stop mode, external interrupt input
by P0 and P2.0 generates the reset signal.
5. When RESET Control Bit (smart option @ 03FH) are set to ‘0’ and chip is in stop mode or abnormal state, the
falling edge input of P0 generates the reset signal regardless of external interrupt enable/disable.
8-2