Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE
Vectors(14) Sources(17)Levels(7)
IRQ0
Timer 0 match/capture
0
1
Reset/Clear
RESET
100H
Basic timer overflow
FCH
IRQ2 ECH
Counter A
S/W
H/W
H/W
F4H
IRQ1
F6H
0
1
Timer 0 overflowFAH
Timer 1 match/capture
Timer 1 overflow
S/W
H/W
H/W
IRQ4
D0H
P2.0 external interrupt
E6H P0.3 external interrupt
IRQ6
E4H P0.2 external interrupt
3
E2H
E0H
2
1
0
P0.1 external interrupt
P0.0 external interrupt
S/W
S/W
S/W
S/W
S/W
IRQ7
E8H
P0.7 external interrupt
P0.6 external interrupt
P0.5 external interrupt
P0.4 external interrupt
S/W
S/W
S/W
S/W
F0H
IRQ3
F2H
Timer 2 match/capture
Timer 2 overflow
S/W
H/W
1
0
Figure 5-2. S3F80P5 Interrupt Structure
NOTE: Reset interrupt vector address (Basic timer overflow) can be varied by smart option.
5-3