Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
ADDRESSING MODES S3F80P5_UM_ REV1.00
T2CON − Timer 2 Control Register E8H Set1 Bank1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
0 0 0 0 0 0 0 0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode
Register addressing mode only
.7 and .6 Timer 2 Input Clock Selection Bits
00
f
OSC
/4
01
f
OSC
/8
10
f
OSC
/16
1 1 Internal clock (counter A flip-flop, T-FF)
.5 and .4 Timer 2 Operating Mode Selection Bits
0 0 Interval timer mode (counter cleared by match signal)
0 1 Capture mode (rising edges, counter running, OVF can occur)
1 0 Capture mode (falling edges, counter running, OVF can occur)
1 1 Capture mode (rising and falling edges, counter running, OVF can occur)
.3 Timer 2 Counter Clear Bit
0 No effect (when write)
1 Clear T2 counter, T2CNT (when write)
.2 Timer 2 Overflow Interrupt Enable Bit (note)
0 Disable T2 overflow interrupt
1 Enable T2 overflow interrupt
.1 Timer 2 Match/Capture Interrupt Enable Bit
0 Disable T2 match/capture interrupt
1 Enable T2 match/capture interrupt
.0 Timer 2 Match/Capture Interrupt Pending Flag Bit
0 No T2 match/capture interrupt pending (when read)
0 Clear T2 match/capture interrupt pending condition (when write)
1 T2 match/capture interrupt is pending (when read)
1 No effect (when write)
NOTE: A timer 2 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 2 match/
capture interrupt, IRQ3, vector F2H, must be cleared by the interrupt service routine (S/W).
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