USER’S MANUAL S3F80P5X S3F80P5 MICROCONTROLLERS April 2010 REV 1.00 Confidential Proprietary of Samsung Electronics Co., Ltd Copyright © 2009 Samsung Electronics, Inc.
Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.
Preface The S3F80P5 Microcontroller User's Manual is designed for application designers and programmers who are using the S3F80P5 microcontroller for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, and address spaces.
Table of Contents Part I — Programming Model Chapter 1 Product Overview S3C8/S3F8-Series Microcontrollers..............................................................................................................1-1 S3F80P5 Microcontroller...............................................................................................................................1-1 Features ................................................................................................................................
Table of Contents (Continued) Chapter 3 Addressing Modes Overview ....................................................................................................................................................... 3-1 Register Addressing Mode (R) ............................................................................................................... 3-2 Indirect Register Addressing Mode (IR) .................................................................................................
Table of Contents(Continued) Chapter 6 Instruction Set Overview........................................................................................................................................................6-1 Data Types..............................................................................................................................................6-1 Register Addressing...................................................................................................................
Table of Contents (Continued) Part II Hardware Descriptions Chapter 9 I/O Ports Overview ....................................................................................................................................................... 9-1 Port Data Registers ................................................................................................................................ 9-3 Pull-Up Resistor Enable Registers .............................................................................
Table of Contents (Continued) Chapter 12 Counter A Overview........................................................................................................................................................12-1 Counter A Control Register (CACON) ....................................................................................................12-3 Counter A Pulse Width Calculations.......................................................................................................
Table of Contents (Conclude) Chapter 15 Lower Voltage Detector Overview ....................................................................................................................................................... 15-1 LVD......................................................................................................................................................... 15-1 LVD FLAG .............................................................................................................
List of Figures Figure Number Title Page Number 1-1 1-2 1-3 1-4 1-5 1-6 1-7 Block Diagram (24-pin) .............................................................................................. 1-3 Pin Assignment Diagram (24-Pin SOP/SDIP Package) ............................................ 1-4 Pin Circuit Type 1 (Port 0) .......................................................................................... 1-6 Pin Circuit Type 2 (Port 1) .............................................................
List of Figures (Continued) Figure Number Title Page Number 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 S3C8/S3F8-Series Interrupt Types ............................................................................5-2 S3F80P5 Interrupt Structure.......................................................................................5-3 ROM Vector Address Area .........................................................................................5-4 Interrupt Function Diagram......................................
List of Figures (Conclude) Figure Number Title Page Number 12-1 12-2 12-3 12-4 Counter A Block Diagram........................................................................................... 12-2 Counter A Control Register (CACON) ....................................................................... 12-3 Counter A Registers ................................................................................................... 12-3 Counter A Output Flip-Flop Waveforms in Repeat Mode ....................
List of Tables Table Number Title Page Number 1-1 Pin Descriptions of 24-SOP/SDIP .............................................................................. 1-5 2-1 The Summary of S3F80P5 Register Type ................................................................. 2-5 4-1 4-1 4-2 4-3 Mapped Registers (Bank0, Set1) ............................................................................... 4-2 Mapped Registers (Continued) ....................................................................
List of Tables(Conclude) Table Number Title Page Number 18-1 18-2 Descriptions of Pins Used to Read/Write the Flash ROM..........................................18-3 Operating Mode Selection Criteria .............................................................................18-4 19-1 19-2 Components of TB80PB.............................................................................................19-4 Setting of the Jumper in TB80PB ...............................................................
S3F80P5_UM_ REV1.00 1 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8/S3F8-SERIES MICROCONTROLLERS Samsung's S3C8/S3F8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various flash memory ROM sizes.
PRODUCT OVERVIEW S3F80P5_UM_ REV1.
S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW BLOCK DIAGRAM (24-PIN PACKAGE) Figure 1-1.
PRODUCT OVERVIEW S3F80P5_UM_ REV1.00 PIN ASSIGNMENTS Vss Xin Xout TEST SDAT/P0.0/INT0 SCLK/P0.1/INT1 nRESET/P0.2/INT2 P0.3/INT3 P0.4/INT4 P0.5/INT4 P0.6/INT4 P0.7/INT4 1 2 3 4 5 6 7 8 9 10 11 12 S3C80P5 24-SOP/SDIP (TOP VIEW) 24 23 22 21 20 19 18 17 16 15 14 13 VDD P2.0/INT5 P3.1/REM/T0CK P3.0/T0PWM/T0CAP/T1CAP/T2CAP P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 Figure 1-2.
S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW Table 1-1. Pin Descriptions of 24-SOP/SDIP Pin Names Pin Type Circuit Type 28 Pin No. Shared Functions P0.0−P0.7 I/O I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors are assignable by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. SED&R (note) circuit built in P0 for STOP releasing. In the tool mode, P0.
PRODUCT OVERVIEW S3F80P5_UM_ REV1.00 PIN CIRCUITS VDD Pull-Up Resistor (67kΩ- typ) Pull-up Enable VDD Data INPUT/OUTPUT Output Disable VSS External Interrupt Noise Filter Stop Release Stop Figure 1-3.
S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW PIN CIRCUITS (Continued) VDD Pull-up Resistor (67kΩ-Typ) Pull-up Enable VDD Data INPUT/OUTPUT Open-Drain Output Disable VSS Normal Input Noise Filter Figure 1-4.
PRODUCT OVERVIEW S3F80P5_UM_ REV1.00 PIN CIRCUITS (Continued) VDD Pull-Up Resistor (67kΩ- typ) Pull-up Enable VDD Data INPUT/ OUTPUT Open-Drain Output Disable VSS External Interrupt Noise Filter Figure 1-5.
S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW PIN CIRCUITS (Continued) VDD Pull-up Resistor (67kΩ-Typ) Pull-up Enable P3CON.2 VDD Port 3.0 Data T0_PWM M U X Data P3.0/T0PWM/T0CAP/ T1CAP/T2CAP Open-Drain Output Disable VSS P3.0 Input P3CON.2,6,7 T0CAP/T1CAP/T2CAP M U X Noise filter Figure 1-6. Pin Circuit Type 4 (P3.
PRODUCT OVERVIEW S3F80P5_UM_ REV1.00 PIN CIRCUITS (Continued) VDD Pull-up Resistor (67kΩ-Typ) Pull-up Enable P3CON.5 VDD M U X Port 3.1 Data Carrier On/Off (P3DAT.7) CACON.2 Data P3.1/REM/T0CK Open-Drain Output Disable VSS P3.1 Input P3CON.5,6,7 T0CK M U X Noise filter Figure 1-7. Pin Circuit Type 5 (P3.
S3F80P5_UM_ REV1.00 2 ADDRESS SPACE ADDRESS SPACE OVERVIEW The S3F80P5 microcontroller has two types of address space: — Internal program memory (Flash memory) — Internal register file A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file. The S3F80P5 has a programmable internal 18-Kbytes Flash ROM. An external memory interface is not implemented.
ADDRESS SPACE S3F80P5_UM_ REV1.00 PROGRAM MEMORY Program memory stores program code or table data. The S3F80P5 has 18-Kbyte of internal programmable Flash memory. The program memory address range is therefore 0000H–47FFH of Flash memory (See Figure 2-1). The first 256 bytes of the program memory (0H–0FFH) are reserved for interrupt vector addresses. Unused locations (0000H – 00FFH except 03CH, 03DH, 03EH and 03FH) in this address range can be used as normal program memory.
S3F80P5_UM_ REV1.00 ADDRESS SPACE SMART OPTION Smart option is the program memory option for starting condition of the chip. The program memory addresses used by smart option are from 003CH to 003FH. The S3F80P5 only use 003EH and 003FH. User can write any value in the not used addresses (003CH and 003DH). The default value of smart option bits in program memory is 0FFH (Normal reset vector address 100H, ISP protection disable).
ADDRESS SPACE S3F80P5_UM_ REV1.00 NOTES 1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP area. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless. 2. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘0’, user must change ISP reset vector address from 0100H to some address which user want to set reset address (0200H, 0300H, 0500H or 0900H).
S3F80P5_UM_ REV1.00 ADDRESS SPACE REGISTER ARCHITECTURE In the S3F80P5 implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area. In case of S3F80P5 the total number of addressable 8-bit registers is 333.
ADDRESS SPACE S3F80P5_UM_ REV1.00 Set 1 Set 2 Bank1 FFH 64 Bytes Bank 0 System and Peripheral Control Register (Register Addressing Mode) E0H DFH D0H CFH System Register (Register Addressing Mode) 32 Bytes Page 0 E0H General Purpose Data Register 32 Bytes (Indirect Register or Indexed Addressing Modes or Stack Operations) FFH 256 Bytes Working Register (Working Register Addressing only) C0H C0H BFH Page 0 192 Bytes Prime Data Register (All Addressing Mode) 00H Figure 2-3.
S3F80P5_UM_ REV1.00 ADDRESS SPACE REGISTER PAGE POINTER (PP) The S3C8/S3F8-series architecture supports the logical expansion of the physical 333-byte internal register files (using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer PP (DFH, Set 1, and Bank0). In the S3F80P5 microcontroller, a paged register file expansion is not implemented and the register page pointer settings therefore always point to “page 0”.
ADDRESS SPACE S3F80P5_UM_ REV1.00 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH. The upper 32-byte area of this 64-byte space (E0H–FFH) is divided into two 32-byte register banks, bank 0 and bank 1. The set register bank instructions SB0 or SB1 are used to address one bank or the other. In the S3F80P5 microcontroller, bank 1 is implemented. The set register bank instructions, SB0 or SB1, are used to address one bank or the other.
S3F80P5_UM_ REV1.00 ADDRESS SPACE PRIME REGISTER SPACE The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) are called the prime register space or, more simply, the prime area. You can access registers in this address using any addressing mode. (In other words, there is no addressing mode restriction for these registers, as is the case for set 1 and set 2 registers.). The prime register area on page 0 is immediately addressable following a reset.
ADDRESS SPACE S3F80P5_UM_ REV1.00 WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as consisting of 32 8-byte register groups or "slices." Each slice consists of eight 8-bit registers.
S3F80P5_UM_ REV1.00 ADDRESS SPACE USING THE REGISTER POINTERS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH. To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction (see Figures 2-6 and 2-7).
ADDRESS SPACE S3F80P5_UM_ REV1.00 F7H (R7) 8-Byte Slice F0H (R0) Register File Contains 32 8-Byte Slices 1 1 1 1 0 X X X 16-byte non-contiguous working register block RP0 07H (R15) 0 0 0 0 0 X X X 8-Byte Slice 00H (R0) RP1 Figure 2-8. Non-Contiguous 16-Byte Working Register Block PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H–85H using the register pointer.
S3F80P5_UM_ REV1.00 ADDRESS SPACE REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access all locations in the register file except for set 2.
ADDRESS SPACE S3F80P5_UM_ REV1.00 Special-Purpose Registers Bank 1 General-Purpose Registers Bank 0 FFH FFH Control Registers E0H Set 2 System Registers D0H CFH C0H BFH C0H RP1 Register Pointers RP0 Each register pointer (RP) can independently point to one of the 24 8-byte "slices" of the register file (other than set 2). After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH (that is, to the com m on working register area).
S3F80P5_UM_ REV1.00 ADDRESS SPACE COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–CFH, as the active 16-byte working register block: RP0 → C0H–C7H RP1 → C8H–CFH This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file.
ADDRESS SPACE S3F80P5_UM_ REV1.00 PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only.
S3F80P5_UM_ REV1.00 ADDRESS SPACE RP0 RP1 Selects RP0 or RP1 Address OPCODE 4-bit address procides three low-order bits Register pointer provides five high-order bits Together they create an 8-bit register address Figure 2-12. 4-Bit Working Register Addressing RP1 RP0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 Selects RP0 0 1 1 1 0 1 1 0 Register address (76H) R6 OPCODE 0 1 1 0 1 1 1 0 Instruction: 'INC R6' Figure 2-13.
ADDRESS SPACE S3F80P5_UM_ REV1.00 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value 1100B. This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register addressing.
S3F80P5_UM_ REV1.00 ADDRESS SPACE RP1 RP0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 0 0 Selects RP1 R11 1 1 0 0 1 0 1 1 8-bit address from instruction 'LD R11, R2' Specifies working register addressing Register address (0ABH) 1 0 1 0 1 0 1 1 Figure 2-15.
ADDRESS SPACE S3F80P5_UM_ REV1.00 SYSTEM AND USER STACKS S3C8-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3F80P5 architecture supports stack operations in the internal register file. Stack Operations Return addresses for procedure calls, interrupts and data are stored on the stack.
S3F80P5_UM_ REV1.
ADDRESS SPACE S3F80P5_UM_ REV1.
S3F80P5_UM_ REV1.00 3 ADDRESSING MODES ADDRESSING MODES OVERVIEW The program counter is used to fetch instructions that are stored in program memory for execution. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory.
ADDRESSING MODES S3F80P5_UM_ REV1.00 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing because it uses a register pointer to specify an 8byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).
S3F80P5_UM_ REV1.00 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space, if implemented (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register.
ADDRESSING MODES S3F80P5_UM_ REV1.00 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory Example Instruction References Program Memory dst OPCODE Register Pair Points to Register Pair Program Memory Sample Instructions: CALL JP @RR2 @RR2 Value used in instruction OPERAND Figure 3-4.
S3F80P5_UM_ REV1.00 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 ~ Program Memory 4-bit Working Register Address dst src OPCODE ~ 3 LSBs Point to the Woking Register (1 of 8) ADDRESS ~ Sample Instruction: OR R3, @R6 Value used in instruction Selected RP points to start of woking register block ~ OPERAND Figure 3-5.
ADDRESSING MODES S3F80P5_UM_ REV1.
S3F80P5_UM_ REV1.00 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3–7). You can use Indexed addressing mode to access locations in the internal register file or in external memory (if implemented). You cannot, however, access locations C0H–FFH in set 1 using indexed addressing.
ADDRESSING MODES S3F80P5_UM_ REV1.
S3F80P5_UM_ REV1.
ADDRESSING MODES S3F80P5_UM_ REV1.00 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
S3F80P5_UM_ REV1.00 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Sample Instructions: JP CALL C,JOB1 DISPLAY ; ; Where JOB1 is a 16-bit immediate address Where DISPLAY is a 16-bit immediate address Figure 3-11.
ADDRESSING MODES S3F80P5_UM_ REV1.00 INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed. Only the CALL instruction can use the Indirect Address mode.
S3F80P5_UM_ REV1.00 ADDRESSING MODES RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction.
ADDRESSING MODES S3F80P5_UM_ REV1.00 IMMEDIATE MODE (IM) In Immediate (IM) mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers. Program Memory OPERAND OPCODE (The operand value is in the instruction) Sample Instruction: LD R0,#0AAH Figure 3-14.
S3F80P5_UM_ REV1.00 4 CONTROL REGISTERS CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3F80P5 control registers are presented in an easy-to-read format. You can use this section as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format. Control register descriptions are arranged in alphabetical order (A~Z) according to the register mnemonic.
CONTROL REGISTERS S3F80P5_UM_ REV1.00 Table 4-1.
S3F80P5_UM_ REV1.00 CONTROL REGISTERS Table 4-1.
CONTROL REGISTERS S3F80P5_UM_ REV1.00 Table 4-2.
S3F80P5_UM_ REV1.00 CONTROL REGISTERS Bit number(s) that is/are appended to the register name for bit addressing Register mnemonic Full register name Name of individual bit or bit function Register address (Hexadecimal) D5H FLAGS - System Flags Register Bit Identifier Reset Value Read/Write .7 Register address (Set ) Register address (Bank ) Set1 Bank0 .7 .6 .5 .4 .3 .2 .1 .0 x R/W x R/W x R/W x R/W x R/W x R/W 0 R/W 0 R/W Carry Flag Bit (C) .
CONTROL REGISTERS S3F80P5_UM_ REV1.00 BTCON — Basic Timer Control Register D3H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7− .4 Watchdog Timer Function Enable Bits (for System Reset) 1 .3 and .2 .1 .
S3F80P5_UM_ REV1.00 CONTROL REGISTERS CACON — Counter A Control Register F3H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 Counter A Input Clock Selection Bits .5 and .4 .3 .2 .1 .
CONTROL REGISTERS S3F80P5_UM_ REV1.00 CLKCON — System Clock Control Register D4H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7− .5 Not used for S3F80P5 .4 and .3 CPU Clock (System Clock) Selection Bits (1) .2– .
S3F80P5_UM_ REV1.00 CONTROL REGISTERS EMT — External Memory Timing Register (NOTE) FEH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 1 1 1 1 1 0 − Read/Write R/W R/W R/W R/W R/W R/W R/W − Addressing Mode Register addressing mode only .7 External WAIT Input Function Enable Bit .6 .5 and .4 .3 and .2 .1 .
CONTROL REGISTERS S3F80P5_UM_ REV1.00 FLAGS — System Flags Register D5H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x 0 0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Addressing Mode Register addressing mode only .7 Carry Flag Bit (C) .6 .5 .4 .3 .2 .1 .
S3F80P5_UM_ REV1.00 CONTROL REGISTERS FMCON — Flash Memory Control Register EFH Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 − − − 0 Read/Write R/W R/W R/W R/W − − − R/W Addressing Mode Register addressing mode only .7− .4 Flash Memory Mode Selection Bits 0101 Programming mode 1010 Erase mode 0110 Hard Lock mode (NOTE) Others Not used for S3F80P5 .3− .1 Not used for S3F80P5 .
CONTROL REGISTERS S3F80P5_UM_ REV1.00 FMSECH — Flash Memory Sector Address Register(High Byte) ECH Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7− .0 Flash Memory Sector Address (High Byte) Note: The high-byte flash memory sector address pointer value is the higher eight bits of the 16-bit pointer address.
S3F80P5_UM_ REV1.00 CONTROL REGISTERS IMR — Interrupt Mask Register DDH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0.4 .6 0 Disable (mask) 1 Enable (un-mask) Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.3–P0.0 0 Disable (mask) 1 Enable (un-mask) .
CONTROL REGISTERS S3F80P5_UM_ REV1.00 IPH — Instruction Pointer (High Byte) DAH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7− .1 Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8).
S3F80P5_UM_ REV1.00 CONTROL REGISTERS IPR — Interrupt Priority Register Bit Identifier .7 .6 FFH .5 .4 .3 .2 .1 .0 x R/W x R/W x R/W x R/W x R/W Reset Value Read/Write Addressing Mode x x x R/W R/W R/W Register addressing mode only .7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C .
CONTROL REGISTERS S3F80P5_UM_ REV1.00 IRQ — Interrupt Request Register DCH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Addressing Mode Register addressing mode only .7 Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7–P0.4 .6 0 Not pending 1 Pending Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.3–P0.0 0 Not pending 1 Pending .5 Not used for S3F80P5 .
S3F80P5_UM_ REV1.00 CONTROL REGISTERS LVDCON — LVD Control Register E0H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value − − − − − − − 0 Read/Write − − − − − − − R/W Addressing Mode Register addressing mode only .7− .1 Not used for S3F80P5. .0 LVD Flag Indicator Bit 0 VDD ≥ LVD_FLAG Level 1 VDD < LVD_FLAG Level NOTE: When LVD detects LVD_FLAG level, LVDCON.0 flag bit is set automatically. When VDD is upper LVD_FLAG level, LVDCON.
CONTROL REGISTERS S3F80P5_UM_ REV1.00 LVDSEL — LVD Flag Level Selection Register F1H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 − − − − − − Read/Write R/W R/W − − − − − − Addressing Mode Register addressing mode only .7 and .6 LVD Flag Level Selection Bits .5− .0 4-18 0 0 LVD_FLAG Level = 1.88V 0 1 LVD_FLAG Level = 1.98V 1 0 LVD_FLAG Level = 2.53V 1 1 LVD_FLAG Level = 2.73V Not used for S3F80P5.
S3F80P5_UM_ REV1.00 CONTROL REGISTERS P0CONH — Port 0 Control Register (High Byte) E8H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 P0.7/INT4 Mode Selection Bits .5 and .4 .3 and .2 .1 and .
CONTROL REGISTERS P0CONL — S3F80P5_UM_ REV1.00 Port 0 Control Register (Low Byte) E9H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 P0.3/INT3 Mode Selection Bits .5 and .4 .3 and .2 .1 and .
S3F80P5_UM_ REV1.00 CONTROL REGISTERS P0INT — Port 0 External Interrupt Enable Register F1H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P0.7 External Interrupt (INT4) Enable Bit .6 .5 .4 .3 .2 .1 .0 0 Disable interrupt 1 Enable interrupt P0.6 External Interrupt (INT4) Enable Bit 0 Disable interrupt 1 Enable interrupt P0.
CONTROL REGISTERS P0PND — S3F80P5_UM_ REV1.00 Port 0 External Interrupt Pending Register F2H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P0.7 External Interrupt (INT4) Pending Flag Bit (see Note) .6 .5 .4 .3 .2 .1 .0 0 No P0.7 external interrupt pending (when read) 1 P0.7 external interrupt is pending (when read) P0.
S3F80P5_UM_ REV1.00 CONTROL REGISTERS P0PUR — Port 0 Pull-up Resistor Enable Register E7H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P0.7 Pull-up Resistor Enable Bit .6 .5 .4 .3 .2 .1 .0 0 Disable pull-up resistor 1 Enable pull-up resistor P0.6 Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor P0.
CONTROL REGISTERS S3F80P5_UM_ REV1.00 P1CONH — Port 1 Control Register (High Byte) EAH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 P1.7 Mode Selection Bits .5 and .4 .3 and .2 .1 and .0 0 0 C-MOS input mode 0 1 Open-drain output mode 1 0 Push-pull output mode 1 1 C-MOS input with pull up mode P1.
S3F80P5_UM_ REV1.00 CONTROL REGISTERS P1CONL — Port 1 Control Register (Low Byte) EBH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 P1.3 Mode Selection Bits .5 and .4 .3 and .2 .1 and .0 0 0 C-MOS input mode 0 1 Open-drain output mode 1 0 Push-pull output mode 1 1 C-MOS input with pull up mode P1.
CONTROL REGISTERS S3F80P5_UM_ REV1.00 P1OUTPU — Port 1 Output Pull-up Resistor Enable Register F2H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P1.7 Output Mode Pull-up Resistor Enable Bit .6 .5 .4 .3 .2 .1 .0 4-26 0 Disable pull-up resistor 1 Enable pull-up resistor P1.
S3F80P5_UM_ REV1.00 CONTROL REGISTERS P2CONL — Port 2 Control Register (Low Byte) EDH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .1 and .0 P2.
CONTROL REGISTERS S3F80P5_UM_ REV1.00 P2INT — Port 2 External Interrupt Enable Register E5H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .0 P2.
S3F80P5_UM_ REV1.00 CONTROL REGISTERS P2OUTMD — Port 2 Output Mode Selection Register F3H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .0 P2.
CONTROL REGISTERS S3F80P5_UM_ REV1.00 P2PND — Port 2 External Interrupt Pending Register E6H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .0 P2.0 External Interrupt (INT4) Pending Flag Bit 0 No P2.0 external interrupt pending (when read) 1 P2.
S3F80P5_UM_ REV1.00 CONTROL REGISTERS P2PUR — Port 2 Pull-up Resistor Enable Register EEH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .0 P2.
CONTROL REGISTERS S3F80P5_UM_ REV1.00 P3CON — Port 3 Control Register EFH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 Package Selection and Alternative Function Select Bits 0 0 Others .5 .4 and .3 .2 .1 and .0 4-32 24 pin package P3.0: T0PWM/T0CAP/T1CAP, P3.1: REM/ T0CK Not used for S3F80P5 P3.
S3F80P5_UM_ REV1.00 CONTROL REGISTERS NOTES: 1. The port 3 data register, P3, at location E3H, set1, bank0, contains seven bit values which correspond to the following Port 3 pin functions (bit 6 is not used for the S3F80P5) a. Port3, bit 7: carrier signal on (“1”) or off (“0”). b. Port3, bit 1,0: P3.1/REM/T0CK pin, bit 0: P3.0/T0PWM/T0CAP/T1CAP pin. 2. The alternative function enable/disable are enabled in accordance with function selection bit (bit5 and bit2). 3.
CONTROL REGISTERS S3F80P5_UM_ REV1.00 P3OUTPU — Port 3 Output Pull-up Resistor Enable Register F4H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value − − − − − − 0 0 Read/Write − − − − − − R/W R/W Addressing Mode Register addressing mode only .7 and .2 Not used for S3F80P5 .1 P3.1 Output Mode Pull-up Resistor Enable Bit .0 4-34 0 Disable pull-up resistor 1 Enable pull-up resistor P3.
S3F80P5_UM_ REV1.00 PP — CONTROL REGISTERS Register Page Pointer DFH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7− .4 Destination Register Page Selection Bits 0 .3− .
CONTROL REGISTERS S3F80P5_UM_ REV1.00 RESETID — Reset Source Indicating Register F0H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Read/Write − − − R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7− .4 Not used for S3F80P5. .3 Key-in Reset Indicating Bit .2 .1 .
S3F80P5_UM_ REV1.00 CONTROL REGISTERS RP0 — Register Pointer 0 D6H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 1 1 0 0 0 − − − Read/Write R/W R/W R/W R/W R/W − − − Addressing Mode Register addressing mode only .7− .3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 248-byte working register areas in the register file.
CONTROL REGISTERS S3F80P5_UM_ REV1.00 SPL — Stack Pointer (Low Byte) D9H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only. .7− .0 Stack Pointer Address (Low Byte) The SP value is undefined following a reset. STOPCON — Stop Control Register FBH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .
S3F80P5_UM_ REV1.00 CONTROL REGISTERS SYM — System Mode Register DEH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 − − x x x 0 0 Read/Write R/W − − R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Tri-State External Interface Control Bit (note1) 0 Normal operation (disable tri-state operation) 1 Set external interface lines to high impedance (enable tri-state operation) .6 and .5 Not used for S3F80P5 (note2) .4− .
CONTROL REGISTERS S3F80P5_UM_ REV1.00 T0CON — Timer 0 Control Register D2H Set 1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7− .6 Timer 0 Input Clock Selection Bits .5 and .4 .3 .2 .1 .0 0 0 fOSC/4096 0 1 fOSC/256 1 0 fOSC/8 1 1 External clock input (at the T0CK pin, P3.1 or P3.
S3F80P5_UM_ REV1.00 CONTROL REGISTERS T1CON — Timer 1 Control Register FAH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 Timer 1 Input Clock Selection Bits .5 and .4 .3 .2 .1 .
ADDRESSING MODES S3F80P5_UM_ REV1.00 T2CON − Timer 2 Control Register E8H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 Timer 2 Input Clock Selection Bits .5 and .4 .3 .2 .1 .
S3F80P5_UM_ REV1.00 5 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8/S3F8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vector address, the vector priorities are established in hardware. A vector address can be assigned to one or more sources.
INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 INTERRUPT TYPES The three components of the S3C8/S3F8-series interrupt structure described above — levels, vectors, and sources — are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3.
S3F80P5_UM_ REV1.00 Levels(7) RESET INTERRUPT STRUCTURE Vectors(14) Sources(17) 100H 1 FCH 0 IRQ0 FAH F6H IRQ1 F4H IRQ2 IRQ3 F0H IRQ4 E4H IRQ6 E2H E0H IRQ7 0 E8H H/W Timer 0 match/capture S/W Timer 0 overflow H/W Timer 1 match/capture S/W Timer 1 overflow H/W Counter A H/W Timer 2 match/capture S/W Timer 2 overflow H/W P2.0 external interrupt S/W P0.3 external interrupt S/W P0.2 external interrupt S/W P0.1 external interrupt S/W P0.0 external interrupt S/W P0.
INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3F80P5 interrupt structure are stored in the vector address area of the internal program memory ROM, 00H−FFH (See Figure 5-3). You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses). The program reset address in the ROM is 0100H.
S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE Table 5-1. S3F80P5 Interrupt Vectors Vector Address Interrupt Source Decimal Value Hex Value 256 100H Basic timer overflow/POR 252 FCH Timer 0 match/capture 250 FAH Timer 0 overflow 246 F6H Timer 1 match/capture 244 F4H Timer 1 overflow 236 ECH Counter A 242 F2H Timer 2 match/capture 240 F0H Timer 2 overflow 232 E8H P0.
INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur, and according to the established priorities. NOTE The system initialization routine that is executed following a reset must always contain an EI instruction to globally enable the interrupt structure.
S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by a specific interrupt level and source. The system-level control points in the interrupt structure are, therefore: • Global interrupt enable and disable (by EI and DI instructions or by a direct manipulation of SYM.
INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by that peripheral (See Table 5-3). Table 5-3.
S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE SYSTEM MODE REGISTER (SYM) The system mode register, SYM (DEH, Set 1, Bank0), is used to globally enable and disable interrupt processing and to control fast interrupt processing (See Figure 5-5). A reset clears SYM.7, SYM.1, and SYM.0 to "0". The 3-bit value, SYM.4−SYM.2, is for fast interrupt level selection and undetermined values after reset. SYM.6 and SYM5 are not used.
INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (DDH, Set 1, and Bank0) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine. Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on.
S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (FFH, Set 1, Bank 0), is used to set the relative priorities of the interrupt levels used in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine. When more than one interrupt source is active, the source with the highest priority level is serviced first.
INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 Interrupt Priority Register(IPR) FEH, Set 1, Bank 0 , R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Group Priority: Group A 0 = IRQ0 > IRQ1 1 = IRQ0 < IRQ1 D7 D4 D1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Group B 0 = IRQ2 > (IRQ3, IRQ4) 1 = IRQ2 < (IRQ3, IRQ4) = Undefined =B >C> A =A >B>C =B >A>C =C>A> B =C>B> A =A >C> B = Undefined Subgroup B (see note) 0 = IRQ3 > IRQ4 1 = IRQ3 < IRQ4 Not used Group C 0 = IRQ6 > IRQ7 1 = IRQ7 > IRQ6 Figure 5-8.
S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (DCH, Set 1, Bank0), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on.
INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: One type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other type must be cleared by the interrupt service routine. Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs.
S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source. 3. The CPU checks the interrupt level of source. 4. The CPU generates an interrupt acknowledge signal. 5. Interrupt logic determines the interrupt's vector address. 6.
INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (except smart option ROM Cell- 003CH, 003DH, 003EH and 003FH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to the stack. 2. Push the program counter's high-byte value to the stack. 3. Push the FLAG register values to the stack. 4.
S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE FAST INTERRUPT PROCESSING (Continued) Two other system registers support fast interrupt processing: • The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the program counter values), and • When a fast interrupt occurs, the contents of the FLAGS register are stored in an unmapped, dedicated register called FLAGS' (“FLAGS prime”).
INTERRUPT STRUCTURE S3F80P5_UM_ REV1.
S3F80P5_UM_ REV1.00 6 INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions.
INSTRUCTION SET S3F80P5_UM_ REV1.00 Table 6-1.
S3F80P5_UM_ REV1.00 INSTRUCTION SET Table 6-1.
INSTRUCTION SET S3F80P5_UM_ REV1.00 Table 6-1.
S3F80P5_UM_ REV1.00 INSTRUCTION SET Table 6-1.
INSTRUCTION SET S3F80P5_UM_ REV1.00 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and FLAGS.2 are used for BCD arithmetic. The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank address status bit (FLAGS.
S3F80P5_UM_ REV1.00 INSTRUCTION SET FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag. Z Zero Flag (FLAGS.6) For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero.
INSTRUCTION SET S3F80P5_UM_ REV1.00 INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag D Decimal-adjust flag H Half-carry flag 0 Cleared to logic zero 1 Set to logic one * Set or cleared according to operation – Value is unaffected x Value is undefined Table 6-3.
S3F80P5_UM_ REV1.00 INSTRUCTION SET Table 6-4. Instruction Notation Conventions Notation cc Description Actual Operand Range Condition code See list of condition codes in Table 6-6. r Working register only Rn (n = 0–15) rb Bit (b) of working register Rn.b (n = 0–15, b = 0–7) r0 Bit 0 (LSB) of working register Rn (n = 0–15) rr Working register pair RRp (p = 0, 2, 4, ...
INSTRUCTION SET S3F80P5_UM_ REV1.00 Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – 0 1 2 3 4 5 6 7 U 0 DEC R1 DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM BOR r0–Rb P 1 RLC R1 RLC IR1 ADC r1,r2 ADC r1,Ir2 ADC R2,R1 ADC IR2,R1 ADC R1,IM BCP r1.b, R2 P 2 INC R1 INC IR1 SUB r1,r2 SUB r1,Ir2 SUB R2,R1 SUB IR2,R1 SUB R1,IM BXOR r0–Rb E 3 JP IRR1 SRP/0/1 IM SBC r1,r2 SBC r1,Ir2 SBC R2,R1 SBC IR2,R1 SBC R1,IM BTJR r2.
S3F80P5_UM_ REV1.00 INSTRUCTION SET Table 6-5.
INSTRUCTION SET S3F80P5_UM_ REV1.00 CONDITION CODES The op-code of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.
S3F80P5_UM_ REV1.00 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing.
INSTRUCTION SET S3F80P5_UM_ REV1.00 ADC — Add with Carry ADC dst,src Operation: dst ← dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two'scomplement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands.
S3F80P5_UM_ REV1.00 INSTRUCTION SET ADD — Add ADD dst,src Operation: dst ← dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Z: S: V: Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise.
INSTRUCTION SET S3F80P5_UM_ REV1.00 AND — Logical AND AND dst,src Operation: dst ← dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise.
S3F80P5_UM_ REV1.00 INSTRUCTION SET BAND — Bit AND BAND dst,src.b BAND dst.b,src Operation: dst(0) ← dst(0) AND src(b) or dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise.
INSTRUCTION SET S3F80P5_UM_ REV1.00 BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison. Flags: C: Z: S: V: D: H: Unaffected. Set if the two bits are the same; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected.
S3F80P5_UM_ REV1.00 INSTRUCTION SET BITC — Bit Complement BITC dst.b Operation: dst(b) ← NOT dst(b) This instruction complements the specified bit within the destination without affecting any other bits in the destination. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 BITR — Bit Reset BITR dst.b Operation: dst(b) ← 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: opc dst | b | 0 Bytes Cycles Opcode (Hex) Addr Mode dst 2 4 77 rb NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
S3F80P5_UM_ REV1.00 INSTRUCTION SET BITS — Bit Set BITS dst.b Operation: dst(b) ← 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: opc dst | b | 1 Bytes Cycles Opcode (Hex) Addr Mode dst 2 4 77 rb NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
INSTRUCTION SET S3F80P5_UM_ REV1.00 BOR — Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) ← dst(0) OR src(b) or dst(b) ← dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise.
S3F80P5_UM_ REV1.00 INSTRUCTION SET BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src(b) is a "0", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRF instruction is executed. Flags: No flags are affected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b) is a "1", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRT instruction is executed. Flags: No flags are affected.
S3F80P5_UM_ REV1.00 INSTRUCTION SET BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) ← dst(0) XOR src(b) or dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise.
INSTRUCTION SET S3F80P5_UM_ REV1.00 CALL — Call Procedure CALL dst Operation: SP @SP SP @SP PC ← ← ← ← ← SP – 1 PCL SP –1 PCH dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.
S3F80P5_UM_ REV1.00 INSTRUCTION SET CCF — Complement Carry Flag CCF Operation: C ← NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 CLR — Clear CLR dst Operation: dst ← "0" The destination location is cleared to "0". Flags: No flags are affected.
S3F80P5_UM_ REV1.00 INSTRUCTION SET COM — Complement COM dst Operation: dst ← NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Z: S: V: D: H: Set if a "borrow" occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise.
S3F80P5_UM_ REV1.00 INSTRUCTION SET CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA Operation: If dst – src = "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. Otherwise, the instruction immediately following the CPIJE instruction is executed.
INSTRUCTION SET S3F80P5_UM_ REV1.00 CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA Operation: If dst – src "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the CPIJNE instruction is executed.
S3F80P5_UM_ REV1.00 INSTRUCTION SET DA — Decimal Adjust DA dst Operation: dst ← DA dst The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed.
INSTRUCTION SET S3F80P5_UM_ REV1.00 DA — Decimal Adjust DA (Continued) Example: Given: Working register R0 contains the value 15 (BCD), working register R1 contains 27 (BCD), and address 27H contains 46 (BCD): ADD R1,R0 ; C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH DA R1 ; R1 ← 3CH + 06 If addition is performed using the BCD values 15 and 27, the result should be 42.
S3F80P5_UM_ REV1.00 INSTRUCTION SET DEC — Decrement DEC dst Operation: dst ← dst – 1 The contents of the destination operand are decremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 DECW — Decrement Word DECW dst Operation: dst ← dst – 1 The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected.
S3F80P5_UM_ REV1.00 INSTRUCTION SET DI — Disable Interrupts DI Operation: SYM (0) ← 0 Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled. Flags: No flags are affected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 DIV — Divide (Unsigned) DIV dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination. When the quotient is ≥ 28, the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect.
S3F80P5_UM_ REV1.00 INSTRUCTION SET DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst Operation: r ← r – 1 If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC.
INSTRUCTION SET S3F80P5_UM_ REV1.00 EI — Enable Interrupts EI Operation: SYM (0) ← 1 An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction. Flags: No flags are affected.
S3F80P5_UM_ REV1.00 INSTRUCTION SET ENTER — Enter ENTER Operation: SP ← @SP IP ← PC ← IP ← SP – 2 ← IP PC @IP IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer. The program memory word that is pointed to by the instruction pointer is loaded into the PC, and the instruction pointer is incremented by two. Flags: No flags are affected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 EXIT — Exit EXIT Operation: IP SP PC IP ← ← ← ← @SP SP + 2 @IP IP + 2 This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. Flags: No flags are affected.
S3F80P5_UM_ REV1.00 INSTRUCTION SET IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 6F Addr Mode dst src – – The instruction IDLE stops the CPU clock but not the system clock.
INSTRUCTION SET S3F80P5_UM_ REV1.00 INC — Increment INC dst Operation: dst ← dst + 1 The contents of the destination operand are incremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected.
S3F80P5_UM_ REV1.00 INSTRUCTION SET INCW — Increment Word INCW dst Operation: dst ← dst + 1 The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 IRET — Interrupt Return IRET IRET (Normal) IRET (Fast) Operation: FLAGS ← @SP SP ← SP + 1 PC ← @SP SP ← SP + 2 SYM(0) ← 1 PC ↔ IP FLAGS ← FLAGS' FIS ← 0 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0").
S3F80P5_UM_ REV1.00 INSTRUCTION SET JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ← dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair.
INSTRUCTION SET S3F80P5_UM_ REV1.00 JR — Jump Relative JR cc,dst Operation: If cc is true, PC ← PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed. (See list of condition codes).
S3F80P5_UM_ REV1.00 INSTRUCTION SET LD — Load LD dst,src Operation: dst ← src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected.
INSTRUCTION SET S3F80P5_UM_ REV1.
S3F80P5_UM_ REV1.00 INSTRUCTION SET LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0) ← src(b) or dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: No flags are affected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ← src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number for data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src 1.
S3F80P5_UM_ REV1.00 INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H.
INSTRUCTION SET S3F80P5_UM_ REV1.00 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst ← src rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected.
S3F80P5_UM_ REV1.00 INSTRUCTION SET LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst ← src rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src Operation: rr ← rr – 1 dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented. The contents of the source location are then loaded into the destination location. The contents of the source are unaffected.
S3F80P5_UM_ REV1.00 INSTRUCTION SET LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src Operation: rr ← rr + 1 dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented. The contents of the source location are loaded into the destination location. The contents of the source are unaffected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 LDW — Load Word LDW dst,src Operation: dst ← src The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: No flags are affected.
S3F80P5_UM_ REV1.00 INSTRUCTION SET MULT — Multiply (Unsigned) MULT dst,src Operation: dst ← dst × src The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. Both operands are treated as unsigned integers. Flags: C: Z: S: V: D: H: Set if result is > 255; cleared otherwise. Set if the result is "0"; cleared otherwise.
INSTRUCTION SET S3F80P5_UM_ REV1.00 NEXT — Next NEXT Operation: PC ← @ IP IP ← IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) 1 10 0F opc Example: The following diagram shows one example of how to use the NEXT instruction.
S3F80P5_UM_ REV1.00 INSTRUCTION SET NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 FF When the instruction NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time.
INSTRUCTION SET S3F80P5_UM_ REV1.00 OR — Logical OR OR dst,src Operation: dst ← dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise.
S3F80P5_UM_ REV1.00 INSTRUCTION SET POP — Pop From Stack POP dst Operation: dst ← @SP SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst ← src IR ← IR – 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented. Flags: No flags are affected.
S3F80P5_UM_ REV1.00 INSTRUCTION SET POPUI — Pop User Stack (Incrementing) POPUI dst,src Operation: dst ← src IR ← IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented. Flags: No flags are affected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 PUSH — Push To Stack PUSH src Operation: SP ← SP – 1 @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: No flags are affected.
S3F80P5_UM_ REV1.00 INSTRUCTION SET PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src Operation: IR ← IR – 1 dst ← src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer. Flags: No flags are affected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR ← IR + 1 dst ← src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer. Flags: No flags are affected.
S3F80P5_UM_ REV1.00 INSTRUCTION SET RCF — Reset Carry Flag RCF RCF Operation: C ← 0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 CF Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero.
INSTRUCTION SET S3F80P5_UM_ REV1.00 RET — Return RET Operation: PC ← @SP SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value. Flags: No flags are affected.
S3F80P5_UM_ REV1.00 INSTRUCTION SET RL — Rotate Left RL dst Operation: C ← dst (7) dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag. 7 0 C Flags: C: Z: S: V: D: H: Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise.
INSTRUCTION SET S3F80P5_UM_ REV1.00 RLC — Rotate Left Through Carry RLC dst Operation: dst (0) ← C C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero. 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise.
S3F80P5_UM_ REV1.00 INSTRUCTION SET RR — Rotate Right RR dst Operation: C ← dst (0) dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C). 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0"; cleared otherwise.
INSTRUCTION SET S3F80P5_UM_ REV1.00 RRC — Rotate Right Through Carry RRC dst Operation: dst (7) ← C C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB). 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the least significant bit position (bit zero) was "1".
S3F80P5_UM_ REV1.00 INSTRUCTION SET SB0 — Select Bank 0 SB0 Operation: BANK ← 0 The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. Flags: No flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 4F The statement SB0 clears FLAGS.0 to "0", selecting bank 0 register addressing.
INSTRUCTION SET S3F80P5_UM_ REV1.00 SB1 — Select Bank 1 SB1 Operation: BANK ← 1 The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some S3F8-series microcontrollers.) Flags: No flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 5F The statement SB1 sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented.
S3F80P5_UM_ REV1.00 INSTRUCTION SET SBC — Subtract With Carry SBC dst,src Operation: dst ← dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand.
INSTRUCTION SET S3F80P5_UM_ REV1.00 SCF — Set Carry Flag SCF Operation: C ← 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: opc Example: The statement SCF sets the carry flag to logic one.
S3F80P5_UM_ REV1.00 INSTRUCTION SET SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ← dst (7) C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. 7 6 0 C Flags: C: Z: S: V: D: H: Set if the bit shifted from the LSB position (bit zero) was "1".
INSTRUCTION SET S3F80P5_UM_ REV1.00 SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) ← src (3–7) If src (1) = 0 and src (0) = 1 then: RP1 (3–7) ← src (3–7) If src (1) = 0 and src (0) = 0 then: RP0 (4–7) ← src (4–7), RP0 (3) ← 0 RP1 (4–7) ← src (4–7), RP1 (3) ← 1 The source data bits one and zero (LSB) determine whether to write one or both of the register pointers, RP0 and RP1.
S3F80P5_UM_ REV1.00 INSTRUCTION SET STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts.
INSTRUCTION SET S3F80P5_UM_ REV1.00 SUB — Subtract SUB dst,src Operation: dst ← dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand. Flags: C: Z: S: V: Set if a "borrow" occurred; cleared otherwise. Set if the result is "0"; cleared otherwise.
S3F80P5_UM_ REV1.00 INSTRUCTION SET SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) ↔ dst (4 – 7) The contents of the lower four bits and upper four bits of the destination operand are swapped. 7 Flags: C: Z: S: V: D: H: 4 3 0 Undefined. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Undefined. Unaffected. Unaffected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result.
S3F80P5_UM_ REV1.00 INSTRUCTION SET TM — Test Under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Flags: C: Z: S: V: D: H: Unaffected.
INSTRUCTION SET S3F80P5_UM_ REV1.00 WFI — Wait For Interrupt WFI Operation: The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt . Flags: No flags are affected.
S3F80P5_UM_ REV1.00 INSTRUCTION SET XOR — Logical Exclusive OR XOR dst,src Operation: dst ← dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise.
INSTRUCTION SET S3F80P5_UM_ REV1.
S3F80P5_UM_ REV1.00 7 CLOCK AND POWER CIRCUITS CLOCK AND POWER CIRCUITS OVERVIEW The clock frequency for the S3F80P5 can be generated by an external crystal or supplied by an external clock source. The clock frequency for the S3F80P5 can range from 1MHz to 8 MHz. The maximum CPU clock frequency, as determined by CLKCON register, is 8 MHz. The XIN and XOUT pins connect the external oscillator or clock source to the on-chip clock circuit.
CLOCK AND POWER CIRCUITS S3F80P5_UM_ REV1.00 C1 XIN C2 XOUT Figure 7-1. Main Oscillator Circuit (External Crystal or Ceramic Resonator) External Clock XIN Open Pin XOUT Figure 7-2.
S3F80P5_UM_ REV1.00 CLOCK AND POWER CIRCUITS CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. When stop mode is released, the oscillator starts by a reset operation or by an external interrupt. To enter the stop mode, STOPCON (STOP Control Register) has to be loaded with value, #0A5H before STOP instruction execution.
CLOCK AND POWER CIRCUITS S3F80P5_UM_ REV1.00 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in address D4H, Set1, Bank0. It is read/write addressable and has the following functions: — Oscillator frequency divide-by value The CLKCON.7– .5 and CLKCON.2- .0 Bit are not used in S3F80P5. After a reset, the main oscillator is activated, and the fOSC/16 (the slowest clock speed) is selected as the CPU clock.
S3F80P5_UM_ REV1.00 CLOCK AND POWER CIRCUITS VDD R1 VDD C1 C2 Figure 7-5. Power Circuit (VDD) Typically, application systems have a resister and two separate capacitors across the power pins. R1 and C1 located as near to the MCU power pins as practical to suppress high-frequency noise. C2 should be a bulk electrolytic capacitor to provide bulk charge storage for the overall system. We recommend that R1=10ohm, C1=0.1uF and C2=100uF. VDD VF VBAT (3.6V) (Note 2) VBAT (1.
CLOCK AND POWER CIRCUITS S3F80P5_UM_ REV1.
S3F80P5_UM_ REV1.00 8 RESET RESET OVERVIEW Resetting the MCU is the function to start processing by generating reset signal using several reset schemes. During reset, most control and status are forced to initial values and the program counter is loaded from the reset vector. In case of S3F80P5, reset vector can be changed by smart option. (Refer to the page 2-3 or 13-4).
RESET S3F80P5_UM_ REV1.00 STOP LVD IPOR Watchdog Timer 1 2 3 RESET 4 5 P0&P2.0 (INT0-INT5) (EI)external interrupt enable RESET Contorl Bit '1' STOP P0 RESET Contorl Bit '1' *RESET Control Bit : smart option bit[0]@03FH STOP Figure 8-1. RESET Sources of the S3F80P5 1. The rising edge detection of LVD circuit while rising of VDD passes the level of VLVD. 2. When POR circuit detects VDD below VPOR, reset is generated by internal power-on reset. 3. Basic Timer over-flow for watchdog timer.
S3F80P5_UM_ REV1.00 RESET Enable/ Disable STOP STOPCON Falling Edge Detector LVD Back-up Mode Rising Edge Detector IPOR BT (WDT) fosc RESET RESET Contorl Bit'1' STOP STOPCON P0& P2.0 P0&P2.0 (INT0~INT5) External Interrupt Control Block Enabled INT0~INT5 Noise Filter P0 SED&R Circuit Falling Edge STOPCON STOP RESET Contorl Bit'1' *RESET Control Bit: smart option bit[0] @03FH Figure 8-2.
RESET S3F80P5_UM_ REV1.00 RESET MECHANISM The interlocking work of reset pin and LVD circuit supplies two operating modes: back-up mode input, and system reset input. Back-up mode input automatically creates a chip stop state when the voltage at VDD is lower than VLVD. When the LVD circuit detects rising edge of VDD on the point VLVD, the reset pulse generator makes a reset pulse, and system reset occurs.
S3F80P5_UM_ REV1.00 RESET INTERNAL POWER-ON RESET The power-on reset circuit is built on the S3F80P5 product. When power is initially applied to the MCU, or when VDD drops below the VPOR, the POR circuit holds the MCU in reset until VDD has risen above the VLVD level. tWAIT Normal Operating Mode VDD VLVD VPOR Reset Pulse Internal RESET Release Figure 8-4.
RESET S3F80P5_UM_ REV1.00 If "Vreset > VIH", the operating status is in STOP mode, LVD circuit is disabled in the S3F80P5X. Stop Mode (LVD off) Reset Low t WAIT (4096x16x1/fosc) Normal Operating Mode (LVD on) VDD VLVD VPOR Reset pulse generated, Oscillation starts POR detected POR Reset Release LVD Reset Release Internal Reset Release Figure 8-5.
S3F80P5_UM_ REV1.00 RESET STOP ERROR DETECTION & RECOVERY When RESET Control Bit (smart option bit [0] @ 03FH) is set to ‘0’ and chip is in stop or abnormal state, the falling edge input of P0 generates the reset signal. Refer to following table and figure for more information. Table 8-1.
RESET S3F80P5_UM_ REV1.00 POWER-DOWN MODES The power down mode of S3F80P5 are described following that: — Idle mode — Back- up mode — Stop mode IDLE MODE Idle mode is invoked by the instruction IDLE (op-code 6FH). In Idle mode, CPU operations are halted while some peripherals remain active.
S3F80P5_UM_ REV1.00 RESET BACK-UP MODE For reducing current consumption, S3F80P5 goes into Back-up mode. If a falling level of VDD is detected by LVD circuit on the point of VLVD, chip goes into the back-up mode. CPU and peripheral operation are stopped, but LVD is enabled. Because of oscillation stop, the supply current is reduced. In back-up mode, chip cannot be released from stop state by any interrupt.
RESET S3F80P5_UM_ REV1.00 tWAIT Stop Mode (LVD off) Normal Operating Mode VDD VLVD Key-in VPOR LVD ON Stop Mode (LVD off) Back-up Mode Normal Operating Mode tWAIT VDD VLVD Reset pulse generated, oscillation start VPOR Key-in LVD ON Figure 8-8.
S3F80P5_UM_ REV1.00 RESET STOP MODE STOP mode is invoked by executing the instruction ‘STOP’, after setting the stop control register (STOPCON). In STOP mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the current consumption can be reduced. All system functions stop when the clock "freezes," but data stored in the internal register file is retained. STOP mode can be released in one of two ways: by a system reset or by an external interrupt.
RESET S3F80P5_UM_ REV1.00 SOURCES TO RELEASE STOP MODE Stop mode is released when following sources go active: — System Reset by Internal Power-On Reset (IPOR) — External Interrupt (INT0-INT5) — SED & R circuit Using IPOR to Release STOP Mode Stop mode is released when the system reset signal goes active by internal power-on reset (IPOR). All system and peripheral control registers are reset to their default hardware values and contents of all data registers are unknown states.
S3F80P5_UM_ REV1.00 RESET SED&R (Stop Error Detect and Recovery) The Stop Error Detect & Recovery circuit is used to release stop mode and prevent abnormal - stop mode that can be occurred by battery bouncing. It executes two functions in related to the internal logic of P0. One is releasing from stop status by switching the level of input port (P0) and the other is keeping the chip from entering stop mode when the chip is in abnormal status.
RESET S3F80P5_UM_ REV1.00 SYSTEM RESET OPERATION System reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initialize the internal CPU and peripheral modules. This procedure brings the S3F80P5 into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the reset pulse generator must be held to active level for a minimum time interval after the power supply comes within tolerance.
S3F80P5_UM_ REV1.00 RESET HARDWARE RESET VALUES Tables 8-2 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: — A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. — An 'x' means that the bit value is undefined after a reset.
RESET S3F80P5_UM_ REV1.00 Table 8-2.
S3F80P5_UM_ REV1.00 RESET Table 8-3.
RESET S3F80P5_UM_ REV1.00 Table 8-4.
S3F80P5_UM_ REV1.00 RESET RECOMMENDATION FOR UNUSUED PINS To reduce overall power consumption, please configure unused pins according to the guideline description Table 8-5. Table 8-5. Guideline for Unused Pins to Reduced Power Consumption Pin Name Port 0 Port 1 Port 2.0 P3.0–3.1 TEST Recommend Example ← # 00H or 0FFH ← # 00H or 0FFH • P0PUR ← # 0FFH • Set Input mode Pull-up Resister • No Connection for Pins • P0CONH • Enable • P0CONL • Set Open-Drain Output mode P1 Data Register to #00H.
RESET S3F80P5_UM_ REV1.00 SUMMARY TABLE OF BACK-UP MODE, STOP MODE, AND RESET STATUS For more understanding, please see the below description Table 8-6. Table 8-6. Summary of Each Mode Item/Mode Approach Condition Back-up • VDD is lower than VLVD Reset Status • The rising edge at VDD is detected by LVD circuit. (When VDD ≥ VLVD) • Watch-dog timer overflow signal is activated. • All I/O port is floating status the ports become input mode but is blocked.
S3F80P5_UM_ REV1.00 9 I/O PORTS I/O PORTS OVERVIEW The S3F80P5 microcontroller has four bit-programmable I/O ports, P0, P1, P2, P3. Two ports, P0 and P1, are 8bit ports and P2 is a 1-bit port and P3 is a 2-bit port. This gives a total of 19 I/O pins. Each port is bit-programmable and can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required.
I/O PORTS S3F80P5_UM_ REV1.00 Table 9-1. S3F80P5 Port Configuration Overview (24-SOP) Port Configuration Options Port 0 8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling edges, rising edges, or both edges; all P0 pin circuits have noise filters and interrupt enable/disable register (P0INT) and pending control register (P0PND); Pull-up resistors can be assigned to individual P0 pins using P0PUR register settings.
S3F80P5_UM_ REV1.00 I/O PORTS PORT DATA REGISTERS Table 9-4 gives you an overview of the register locations of all four S3F80P5 I/O port data registers. Data registers for ports 0,1 have the general format shown in Figure 9-1. NOTE The data register for port 3, P3, contains 2-bits for P3.0−P3.1, and an additional status bit (P3.7) for carrier signal on/off. Table 9-2.
I/O PORTS S3F80P5_UM_ REV1.00 PULL-UP RESISTOR ENABLE REGISTERS You can assign pull-up resistors to the pin circuits of individual pins in port0 and port1. To do this, you make the appropriate settings to the corresponding pull-up resistor enable registers; P0PUR. These registers are located in set 1, bank 0 at locations E7H, respectively, and are read/write accessible using Register addressing mode. You can assign a pull-up resistor to the port 3 pins, P3.0 − P3.
S3F80P5_UM_ REV1.00 10 BASIC TIMER and TIMER 0 BASIC TIMER and TIMER 0 OVERVIEW The S3F80P5 has two default timers: the 8-bit basic timer and the 8-bit general-purpose timer/counter. The 8-bit timer/counter is called timer 0. BASIC TIMER (BT) You can use the basic timer (BT) in two different ways: — As a watch-dog timer to provide an automatic reset mechanism in the event of a system malfunction — To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.
BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00 BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watch-dog timer function. It is located in Set 1 and Bank0, addresses D3H, and is read/write addressable using register addressing mode. A reset clears BTCON to '00H'.
S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watch-dog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than '1010B'. (The '1010B' value disables the watch-dog function.) A reset clears BTCON to '00H', automatically enabling the watch-dog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock.
BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.
S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 Timer 0 Control Register (T0CON) D2H, Set 1, Bank0 , R/W MS B .7 .6 .5 .4 .3 .2 .1 .
BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00 TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts (IRQ0, Vectors FAH and FCH) The timer 0 module can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/ capture interrupt (T0INT). T0OVF is interrupt with level IRQ0 and vector FAH. T0INT also belongs to interrupt level IRQ0, but is assigned the separate vector address, FCH.
S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs continuously, overflowing at ‘FFH’, and then continues incrementing from ‘00H’.
BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00 Capture Mode In capture mode, a signal edge that is detected at the T0CAP pin opens a gate and loads the current counter value into the T0 data register. You can select rising or falling edges to trigger this operation. Timer 0 also gives you capture input source: the signal edge at the T0CAP pin. You select the capture input by setting the value of the timer 0 capture input selection bit in the port 3 control register, P3CON.2, (set 1, bank 0, EFH). When P3CON.
S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 Bit 1 RESET or STOP Bits 3, 2 Data Bus Clear 1/16384 1/4096 XIN DIV R MUX 1/1024 8-Bit Up Counter (BTCNT, Read-Only) 1/128 Bit 0 Basic Timer Control Register (Write'1010xxxxB' to disable.) RESET OVF When BTCNT.4 is set after releasing from RESET or STOP mode , CPU clock starts . Bits 7, 6 Bit 2 Data Bus R OVF 1/4096 IRQ0 (Timer0 Overflow) 1/256 XIN DIV 1/8 MUX 8-Bit Up-Counter R (T0CNT) Clear Match (2) Bit 3 Bit 1 P3.
BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.
S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 PROGRAMMING TIP — Programming Timer 0 This sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and determines the execution sequence which follows a timer 0 interrupt.
BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00 PROGRAMMING TIP — Programming Timer 0 (Continued) CP JR BITS NO_200MS_SET: LD POP T0OVER 10-12 IRET R0,#32H ; 50 × 4 = 200 ms ULT,NO_200MS_SET R1.2 ; Bit setting (61.
S3F80P5_UM_ REV1.00 11 TIMER 1 TIMER 1 OVERVIEW The S3F80P5 microcontroller has a 16-bit timer/counter called Timer 1 (T1). For universal remote controller applications, Timer 1 can be used to generate the envelope pattern for the remote controller signal.
TIMER 1 S3F80P5_UM_ REV1.00 TIMER 1 OVERFLOW INTERRUPT Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflow occurs in the 16-bit up counter. When you set the Timer 1 overflow interrupt enable bit, T1CON.2, to “1”, the overflow interrupt is generated each time the 16-bit up counter reaches ‘FFFFH’. After the interrupt request is generated, the counter value is automatically cleared to ‘00H’ and up counting resumes. By writing a “1” to T1CON.
S3F80P5_UM_ REV1.00 TIMER 1 TIMER 1 MATCH INTERRUPT Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit counter value matches the value that is written to the Timer 1 reference data registers, T1DATAH and T1DATAL. When a match condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and up counting resumes from ‘00H’.
TIMER 1 S3F80P5_UM_ REV1.00 T1CON.2 T1CON. 7-.6 IRQ1 OVF CAOF (T-F/F) fOSC/4 fOSC/8 MUX 16-Bit Up-Counter R (Read-Only) fOSC/16 Clear Match (note) 16-Bit Compatator MUX Timer 1 High/Low Buffer Register T1CON.5-.4 T1CON.3 Match Signal T1OVF Timer 1 Data High/Low Register Data Bus NOTE: Match signal is occurrd only in interval mode. Figure 11-3. Timer 1 Block Diagram 11-4 T1CON.3 T1CON.1 T1CON.
S3F80P5_UM_ REV1.00 TIMER 1 TIMER 1 CONTROL REGISTER (T1CON) The Timer 1 control register, T1CON, is located in Set 1, FAH, Bank0 and is read/write addressable.
TIMER 1 S3F80P5_UM_ REV1.00 Timer1 Counter High-byte Register (T1CNTH) F6H, Set 1, Bank 0, R MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Reset Value: 00H Timer 1 Counter Low-byte Register (T1CNTL) F7H, Set 1, Bank 0, R MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Reset Value: 00H Timer 1 Data High-byte Register (T1DATAH) F8H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Reset Value: FFH Timer 1 Data Low-byte Register (T1DATAL) F9H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .
S3F80P5_UM_ REV1.00 12 COUNTER A COUNTER A OVERVIEW The S3F80P5 microcontroller has one 8-bit counter called counter A.
COUNTER A S3F80P5_UM_ REV1.00 CACON.6-.7 DIV 1 DIV 2 MUX CLK 8-Bit Down Counter CACON.0 (CAOF) MUX CACON.3 DIV 4 To Other Block (P3.1/REM) DIV 8 Repeat Control Interrupt Control INT. GEN. Counter A Data Low Byte Register CACON.2 fOSC CACON.4-.5 Counter A Data High Byte Register Data Bus NOTE: The value of the CADATAL register is loaded into the 8-bit counter when the operation of the counter A stars. If a borrow occurs, the value of the CADATAH register is loaded into the 8-bit counter.
S3F80P5_UM_ REV1.00 COUNTER A COUNTER A CONTROL REGISTER (CACON) The counter A control register, CACON, is located in F3H, Set 1, Bank 0, and is read/write addressable. CACON contains control settings for the following functions (See Figure 12-2): — Counter A clock source selection — Counter A interrupt enable/disable — Counter A interrupt pending control (read for status, write to clear) — Counter A interrupt time selection Counter A Control Register (CACON) F3H, Set 1, Bank 0, R/W MSB .7 .6 .5 .
COUNTER A S3F80P5_UM_ REV1.00 COUNTER A PULSE WIDTH CALCULATIONS tLOW tHIGH tLOW To generate the above repeated waveform consisted of low period time, tLOW, and high period time, tHIGH. When CAOF = 0, tLOW = (CADATAL + 2) × 1/Fx. 0H < CADATAL < 100H, where Fx = the selected clock. tHIGH = (CADATAH + 2) × 1/Fx. 0H < CADATAH < 100H, where Fx = the selected clock. When CAOF = 1, tLOW = (CADATAH + 2) × 1/Fx. 0H < CADATAH < 100H, where Fx = the selected clock. tHIGH = (CADATAL + 2) × 1/Fx.
S3F80P5_UM_ REV1.00 COUNTER A 0H 100H 200H 100H 200H Counter A Clock CAOF = '0' CADATAL = 01-FFH CADATAH = 00H High CAOF = '0' CADATAL = 00H CADATAH = 01-FFH Low CAOF = '0' CADATAL = 00H CADATAH = 00H Low CAOF = '1' CADATAL = 00H CADATAH = 00H High 0H Counter A Clock CAOF = '1' CADATAL = DEH CADATAH = 1EH CAOF = '0' CADATAL = DEH CADATAH = 1EH CAOF = '1' CADATAL = 7EH CADATAH = 7EH CAOF = '0' CADATAL = 7EH CADATAH = 7EH E0H 20H E0H 20H 80H 80H 80H 80H Figure 12-4.
COUNTER A S3F80P5_UM_ REV1.00 PROGRAMMING TIP — To generate 38 kHz, 1/3duty signal through P3.1 This example sets Counter A to the repeat mode, sets the oscillation frequency as the Counter A clock source, and CADATAH and CADATAL to make a 38 kHz, 1/3 Duty carrier frequency. The program parameters are: 8.795 us 17.59 us 37.9 kHz 1/3 duty — Counter A is used in repeat mode — Oscillation frequency is 4 MHz (0.25 μs) — CADATAH = 8.795 μs / 0.25 μs = 35.18, CADATAL = 17.59 μs / 0.25 μs = 70.36 — Set P3.
S3F80P5_UM_ REV1.00 COUNTER A PROGRAMMING TIP — To generate a one-pulse signal through P3.1 This example sets Counter A to the one shot mode, sets the oscillation frequency as the Counter A clock source, and CADATAH and CADATAL to make a 40 μs width pulse. The program parameters are: 40 us — Counter A is used in one-shot mode — Oscillation frequency is 4 MHz (1 clock = 0.25 μs) — CADATAH = 40 μs / 0.25 μs = 160, CADATAL = 1 — Set P3.1 C-MOS push-pull output and CAOF mode.
COUNTER A S3F80P5_UM_ REV1.
S3F80P5_UM_ REV1.00 13 TIMER 2 TIMER 2 OVERVIEW The S3F80P5 microcontroller has a 16-bit timer/counter called Timer 2 (T2). For universal remote controller applications, timer 2 can be used to generate the envelope pattern for the remote controller signal.
TIMER 2 S3F80P5_UM_ REV1.00 TIMER 2 OVERFLOW INTERRUPT Timer 2 can be programmed to generate an overflow interrupt (IRQ3, F0H) whenever an overflow occurs in the 16-bit up counter. When you set the timer 2 overflow interrupt enable bit, T2CON.2, to “1”, the overflow interrupt is generated each time the 16-bit up counter reaches ‘FFFFH’. After the interrupt request is generated, the counter value is automatically cleared to ‘00H’ and up counting resumes. By writing a “1” to T2CON.
S3F80P5_UM_ REV1.00 TIMER 2 TIMER 2 MATCH INTERRUPT Timer 2 can also be used to generate a match interrupt (IRQ3, vector F2H) whenever the 16-bit counter value matches the value that is written to the timer 2 reference data registers, T2DATAH and T2DATAL. When a match condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and up counting resumes from ‘00H’.
TIMER 2 S3F80P5_UM_ REV1.00 T2CON.2 T2CON. 7-.6 IRQ3 OVF CAOF (T-F/F) fOSC/4 fOSC/8 MUX 16-Bit Up-Counter R (Read-Only) fOSC/16 Clear Match (note) 16-Bit Compatator MUX Timer 2 High/Low Buffer Register T2CON.5-.4 T1CON.3 Match Signal T2OVF Timer 2 Data High/Low Register Data Bus NOTE: Match signal is occurrd only in interval mode. Figure 13-3. Timer 2 Block Diagram 13-4 T2CON.3 T2CON.1 T1CON.
S3F80P5_UM_ REV1.00 TIMER 2 TIMER 2 CONTROL REGISTER (T2CON) The timer 2 control register, T2CON, is located in address E8H, Bank1, Set 1 and is read/write addressable.
TIMER 2 S3F80P5_UM_ REV1.00 Timer2 Counter High-Byte Register (T2CNTH) E4H , Set 1, Bank 1, Read-only MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Reset Value: 00H Timer 2 Counter Low-Byte Register (T2CNTL) E5H , Set 1, Bank 1, Read-only MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Reset Value: 00H Timer 2 Data High-Byte Register (T2DATAH) E6H , Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Reset Value: FFH Timer 2 Data Low-Byte Register (T2DATAL) E7H , Set 1, Bank 1, R/W MSB .7 .6 .5 .
S3F80P5_UM_ REV1.00 14 EMBEDDED FLASH MEMORY INTERFACE EMBEDDED FLASH MEMORY INTERFACE OVERVIEW The S3F80P5 has an on-chip flash memory internally instead of masked ROM. The flash memory is accessed by instruction ‘LDC’. This is a sector erasable and a byte programmable flash. User can program the data in a flash memory area any time you want. The S3F80P5‘s embedded 18K-byte memory has two operating features as below: — User Program Mode — Tool Program Mode: Refer to the chapter 18.
EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 User Program Mode This mode supports sector erase, byte programming, byte read and one protection mode (Hard Lock Protection). The S3F80P5 has the internal pumping circuit to generate high voltage. Therefore, 12.5V into Vpp (TEST) pin is not needed. To program a flash memory in this mode several control registers will be used.
S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE SMART OPTION Smart option is the program memory option for starting condition of the chip. The program memory addresses used by smart option are from 003CH to 003FH. The S3F80P5 only use 003EH and 003FH. User can write any value in the not used addresses (003CH and 003DH). The default value of smart option bits in program memory is 0FFH (Normal reset vector address 100H, ISP protection disable).
EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 NOTES 1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP area. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless. 2. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘0’, user must change ISP reset vector address from 0100H to some address which user want to set reset address (0200H, 0300H, 0500H or 0900H).
S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE) FLASH MEMORY CONTROL REGISTER (FMCON) FMCON register is available only in user program mode to select the flash memory operation mode; sector erase, byte programming, and to make the flash memory into a hard lock protection. Flash Memory Control Register (FMCON ) EFH , Set 1 , Bank 1 , R/W MS B .7 .6 .5 .4 .3 .2 .1 .
EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 FLASH MEMORY SECTOR ADDRESS REGISTERS There are two sector address registers for the erase or programming flash memory. The FMSECL (Flash Memory Sector Address Register Low Byte) indicates the low byte of sector address and FMSECH (Flash Memory Address Sector Register High Byte) indicates the high byte of sector address. One sector consists of 128-bytes. Each sector’s address starts XX00H or XX80H, that is, a base address of sector is XX00H or XX80H.
S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE SECTOR ERASE User can erase a flash memory partially by using sector erase function only in user program mode. The only unit of flash memory to be erased in the user program mode is a sector. The program memory of S3F80P5, 18Kbytes flash memory, is divided into 144 sectors. Every sector has all 128byte sizes. So the sector to be located destination address should be erased first to program a new data (one byte) into flash memory.
EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 The Sector Erase Procedure in User Program Mode 1. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”. 2. Set Flash Memory Sector Address Register (FMSECH and FMSECL). 3. Set Flash Memory Control Register (FMCON) to “10100001B”. 4. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”.
S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE PROGRAMMING TIP — Sector Erase Case1. Erase one sector • • ERASE_ONESECTOR: SB1 LD LD LD LD ERASE_STOP: LD SB0 FMUSR,#0A5H FMSECH,#40H FMSECL,#00H FMCON,#10100001B ; User program mode enable ; Set sector address 4000H,sector 128, ; among sector 0~511 ; Select erase mode enable & Start sector erase FMUSR,#00H ; User program mode disable s Case2.
EMBEDDED FLASH MEMORY INTERFACE SECTOR_ERASE: LD R12,SecNumH LD R14,SecNumL MULT RR12,#80H MULT RR14,#80H ADD R13,R14 S3F80P5_UM_ REV1.00 ; Calculation the base address of a target sector ; The size of one sector is 128-bytes ; BTJRF FLAGS.
S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE PROGRAMMING A flash memory is programmed in one-byte unit after sector erase. The write operation of programming starts by ‘LDC’ instruction. The program procedure in user program mode 1. Must erase target sectors before programming. 2. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”. 3. Set Flash Memory Control Register (FMCON) to “0101000XB”. 4.
EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 Start SB1 ; Select Bank1 FMSECH FMSECL High Address of Sector Low Address of Sector R(n) R(n+1) R(data) High Address to Write Low Address to Write 8-bit Data FMUSR #0A5H FMCON #01010000B LDC @RR(n),R(data) FMUSR #00H SB0 ; Set Secotr Base Address ; Set Address and Data ; User Program Mode Enable ; Mode Select ; Write data at flash ; User Program Mode Disable ; Select Bank0 Finish 1-BYTE Writing Figure 14-9.
S3F80P5_UM_ REV1.
EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 PROGRAMMING TIP — Programming Case1.
S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE Case3.
EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 READING The read operation starts by ‘LDC’ instruction. The program procedure in user program mode 1. Load a flash memory upper address into upper register of pair working register. 2. Load a flash memory lower address into lower register of pair working register. 3.
S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE HARD LOCK PROTECTION User can set Hard Lock Protection by writing ‘0110B’ in FMCON7-4. This function prevents the changes of data in a flash memory area. If this function is enabled, the user cannot write or erase the data in a flash memory area. This protection can be released by the chip erase execution in the tool program mode. In terms of user program mode, the procedure of setting Hard Lock Protection is following that.
EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.
S3F80P5_UM_ REV1.00 15 LOW VOLTAGE DETECTOR LOW VOLTAGE DETECTOR OVERVIEW The S3F80P5 micro-controller has a built-in Low Voltage Detector (LVD) circuit, which allows LVD and LVD_FLAG detection of power voltage. The S3F80P5 has two options in LVD and LVD_FLAG voltage level according to the operating frequency to be set by smart option (Refer to the page 2-4). Operating Frequency 8MHz: • Low voltage detect level for Backup Mode and Reset (LVD): 1.
LOW VOLTAGE DETECTOR S3F80P5_UM_ REV1.00 NOTES 1. A term of LVD is a symbol of parameter that means ‘Low Level Detect Voltage for Back-Up Mode’. 2. A term of LVD_FLAG is a symbol of parameter that means ‘Low Level Detect Voltage for Flag Indicator’. 3. The voltage gaps (LVD_GAPn (n=1~4)) between LVD and LVD FLAGn(n=1~4) have ± 80mV distribution.
S3F80P5_UM_ REV1.00 LOW VOLTAGE DETECTOR LOW VOLTAGE DETECTOR CONTROL REGISTER (LVDCON) LVDCON.0 is used flag bit to indicate low battery in IR application or others. When LVD circuit detects LVD_FLAG, LVDCON.0 flag bit is set automatically. The reset value of LVDCON is #00H. Low Voltage Detect Control Register (LVDCON ) E 0 H , Set 1, Bank 1, R /W MSB .7 .6 .5 .4 Not used for S .3 .2 .1 .
S3F80P5_UM_ REV1.00 16 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, S3F80P5 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: • Absolute Maximum Ratings • D.C.
ELECTRICAL DATA S3F80P5_UM_ REV1.00 Table 16-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Rating *TBD Unit Supply Voltage VDD − − 0.3 to + 3.8 V Input Voltage VIN − − 0.3 to VDD + 0.3 V Output Voltage VO All output pins − 0.3 to VDD + 0.
S3F80P5_UM_ REV1.00 ELECTRICAL DATA Table 16-2. D.C. Electrical Characteristics (Continued) (TA = -25 °C to + 85 °C, VDD = 1.60 V to 3.6 V) Parameter Output Low Voltage Input High Leakage Current Input Low Leakage Current Symbol VOL1 Conditions VDD = 1.70 V, IOL = 8mA Min Typ Max Unit − 0.4 0.5 V Port 3.1 only VOL2 VDD = 1.70 V, IOL = 5mA P3.0 and P2.0 0.4 0.5 VOL3 VDD = 1.70 V, IOL = 2mA Port0, Port1 0.4 1.
ELECTRICAL DATA S3F80P5_UM_ REV1.00 Table 16-2. D.C. Electrical Characteristics (Continued) (TA = -25 °C to + 85 °C, VDD = 1.60 V to 3.6 V) Parameter Symbol Min Typ Max Operating Mode (note2) VDD = 3.6 V 8 MHz crystal − 3 6 IDD2 Idle Mode VDD =3.6 V 8 MHz crystal − 1 2 IDD3 Stop Mode − 0.7 5 Operating Mode VDD = 3.6 V 4 MHz crystal − 1.5 3 Idle Mode VDD =3.6 V 4 MHz crystal − IDD1 Supply Current (note1) Conditions Unit mA uA LVD OFF, VDD = 3.6 V IDD12 IDD22 mA 0.
S3F80P5_UM_ REV1.00 ELECTRICAL DATA NOTE: The voltage gaps (LVD_GAPn (n=1~4)) between LVD and LVD FLAGn(n=1~4) have ± 80mV distribution. LVD and LVD FLAGn(n=1~4) are not overlapped. The variation of LVD FLAGn(n=1~4) and LVD always is shifted in same direction. That is, if one chip has positive tolerance (e.g. +50mV) in LVD FLAG, LVD has positive tolerance.
ELECTRICAL DATA S3F80P5_UM_ REV1.00 Idle Mode (Basic Timer Active) ~ ~ Stop Mode Data Retention Mode ~ ~ VDD Normal Operating Mode VDDDR Execution of STOP Instrction EXT INT 0.8VDD 0.2VDD tWAIT Figure 16-1.
S3F80P5_UM_ REV1.00 ELECTRICAL DATA Reset Occur Oscillation Stabilization Time Stop Mode Normal Operating Mode Back-up Mode VDD ~ ~ VLVD ~ ~ VDDDR tWAIT Execution of STOP Instrction NOTE: Data Retention Time tWAIT is the same as 4096 x 16 x 1/f OSC. Figure 16-2. Stop Mode Release Timing When Initiated by a LVD Table 16-6.
ELECTRICAL DATA S3F80P5_UM_ REV1.00 tINTL tINTH 0.8 VDD 0.2 VDD NOTE: 0.8 VDD 0.2 VDD The unit tCPU means one CPU clock period. Figure 16-3.
S3F80P5_UM_ REV1.00 ELECTRICAL DATA Table 16-8.
ELECTRICAL DATA S3F80P5_UM_ REV1.00 Table 16-9. Oscillation Stabilization Time (TA = -25 °C to + 85 °C, VDD = 3.6 V) Oscillator Test Condition Min Typ Max Unit Main crystal fOSC > 1 MHz − − 20 ms Main ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range.
S3F80P5_UM_ REV1.00 ELECTRICAL DATA fOSC (Main Oscillator Frequency) Minimun Instruction Clock A 2 MHz 8 MHz 1.5MHz 6 MHz 1MHz 4 MHz 500 kHz 2 MHz 250 kHz 1 MHz 400 kHz 1kHz 1 2 3 4 5 6 7 Supply Voltage (V) Minimun Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, or 16) A: 1.65 V, 8 MHz Figure 16-4. Operating Voltage Range of S3F80P5 Table 16-10.
ELECTRICAL DATA S3F80P5_UM_ REV1.00 Table 16-11. ESD Characteristics Parameter Electrostatic discharge Symbol Conditions Min Typ Max Unit VESD HBM 2000 − − V MM 200 − − V CDM 500 V − − NOTE: If on board programming is needed, it is recommended that add a 0.1uF capacitor between TEST pin and VSS for better noise immunity; otherwise, connect TEST pin to VSS directly.
S3F80P5_UM_ REV1.00 17 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3F80P5 micro-controller is currently available in a 24-pin SOP and SDIP package. 0-8 #13 0.15 2.30 ± 0.10 #12 15.74 MAX 15.34 ± 0.20 + 0.10 - 0.05 0.85 ± 0.20 #1 2.50 MAX 24-SOP-375 9.53 7.50 ± 0.20 10.30 ± 0.30 #24 1.27 (0.69) 0.38 NOTE: + 0.10 - 0.05 0.05 MIN 0.10 MAX Dimensions are in millimeters. Figure 17-1.
MECHANICAL DATA S3F80P5_UM_ REV1.00 #13 0-15 0.2 5 24-SDIP-300 +0 - 0 .10 .05 7.62 6.40 ± 0.20 #24 0.46 ± 0.10 (1.70) NOTE: 0.89 ± 0.10 1.778 5.08 MAX 22.95 ± 0.20 3.30 ± 0.30 23.35 MAX 3.25 ± 0.20 #12 0.51 MIN #1 Dimensions are in millimeters. Figure 17-2.
S3F80P5_UM_ REV1.00 18 S3F80P5 FLASH MCU S3F80P5 FLASH MCU OVERVIEW The S3F80P5 single-chip CMOS microcontroller is the Flash MCU. It has an on-chip Flash MCU ROM. The Flash ROM is accessed by serial data format. NOTE This chapter is about the Tool Program Mode of Flash MCU. If you want to know the User Program Mode, refer to the chapter 14. Embedded Flash Memory Interface.
S3F80P5 FLASH MCU S3F80P5_UM_ REV1.00 Vss Xin Xout TEST SDAT/P0.0/INT0 SCLK/P0.1/INT1 nRESET/P0.2/INT2 P0.3/INT3 P0.4/INT4 P0.5/INT4 P0.6/INT4 P0.7/INT4 1 2 3 4 5 6 7 8 9 10 11 12 S3C80P5 24-SOP/SDIP (TOP VIEW) 24 23 22 21 20 19 18 17 16 15 14 13 VDD P2.0/INT5 P3.1/REM/T0CK P3.0/T0PWM/T0CAP/T1CAP/T2CAP P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 Figure 18-1.
S3F80P5_UM_ REV1.00 S3F80P5 FLASH MCU Table 18-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P0.0 SDAT 5 I/O P0.1 SCLK 6 I Serial clock pin. Input only pin. TEST TEST 4 I Tool mode selection when TEST pin sets Logic value ‘1’. If user uses the flash writer tool mode (ex.spw2+ etc.), user should connect TEST pin to VDD. (S3F80P5 supplies high voltage 12.5V by internal high voltage generation circuit.
S3F80P5 FLASH MCU S3F80P5_UM_ REV1.00 OPERATING MODE CHARACTERISTICS When 3.3 V is supplied to the TEST pin of the S3F80P5, the Flash ROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 22-2 below. Table 18-2. Operating Mode Selection Criteria VDD TEST REG/nMEM 3.3 V 3.3 V 3.3 V 3.3 V 0 0 1 Address (A15–A0) 0000H 0000H 0E3FH NOTE: "0" means Low level; "1" means High level.
S3F80P5_UM_ REV1.00 19 ELECTRICAL DATA DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system on a turnkey basis. The development support system is composed of a host system, debugging tools, and supporting software. For a host system, any standard computer that employs Win95/98/2000/XP as its operating system can be used.
DEVELOPMENT TOOLS S3F80P5_UM_ REV1.00 [Development System Configuration] IBM-PC AT or Compatible RS-232C / USB Emulator [ SK-1200(RS-232,USB) or OPENIce I-500(RS-232) ] Target Application System OTP/MTP Writer Block RAM Break/Display Block Bus Probe Adapter Trace/Timer Block SAM8 Base Block POD Power Supply Block Figure 19-1.
S3F80P5_UM_ REV1.00 ELECTRICAL DATA TB80PB TARGET BOARD TB80PB Rev1 To User _Vcc In-Circuit Emulator (SK-1200,OPENIce I -500) nRESET IDLE STOP U2 74HC11 + + GND On S1 + RESET JP6 JP10 Y1 VDDMCU JP8 VDD_3.
DEVELOPMENT TOOLS S3F80P5_UM_ REV1.00 Table 19-1. Setting of the Jumper in TB80PB JP# Description 1-2 Connection 2-3 Connection NOT connected Default Setting S1 Target board power source Use JP7(VCC) Join 1-2 JP1 Target board mode selection H: Main-Mode L: EVA-Mode Join 2-3 JP2 Operation Mode H: User Mode L: Test-Mode Join 1-2 JP3 MDS version SMDS2 SMDS2+,SK-1200,OPENIce I-500 Join 2-3 Target system is supplied VDD from user system.
S3F80P5_UM_ REV1.00 – ELECTRICAL DATA STOP LED This LED is ON when the evaluation chip (S3E80PB) is in stop mode.
DEVELOPMENT TOOLS S3F80P5_UM_ REV1.00 J2 NOTE: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 50-Pin DIP Connector P2.3/INT8 P2.4/INT9/CIN0 P3.0/T0PWM/T0CAP P3.1/REM VDD VSS XOUT XIN TEST P2.5/INT9/CIN1 P2.6/INT9/CIN2 RESET P3.4 P3.5 P2.7/INT9/CIN3 P1.0 P3.2/T0CK P3.3/T1CAP/T2CAP P4.7 P1.1 P1.2 P1.3 N.C N.C N.C 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 P2.2/INT7 P2.1/INT6 P2.0/INT5 P4.0 P4.1 P4.2 P4.3 P0.7/INT4 P0.6/INT4 P0.5/INT4 P0.4/INT4 P0.3/INT3 P0.2/INT2 P0.
S3F80P5_UM_ REV1.00 ELECTRICAL DATA Third Parties for Development Tools SAMSUNG provides a complete line of development tools for SAMSUNG's microcontroller. With long experience in developing MCU systems, our third parties are leading companies in the tool's technology. SAMSUNG Incircuit emulator solution covers a wide range of capabilities and prices, from a low cost ICE to a complete system with an OTP/MTP programmer.
DEVELOPMENT TOOLS S3F80P5_UM_ REV1.00 OTP/MTP PROGRAMMER (WRITER) SPW-uni SEMINIX Single OTP/ MTP/FLASH Programmer • TEL: 82-2-539-7891 • FAX: 82-2-539-7819. • E-mail: sales@seminix.com • URL: http://www.seminix.com • Download/Upload and data edit function • PC-based operation with USB port • Full function regarding OTP/MTP/FLASH MCU programmer (Read, Program, Verify, Blank, Protection..
S3F80P5_UM_ REV1.00 ELECTRICAL DATA OTP/MTP PROGRAMMER (WRITER) (Continued) US-pro SEMINIX Portable Samsung OTP/MTP/FLASH Programmer • Portable Samsung OTP/MTP/FLASH Programmer • Small size and Light for the portable use • Support all of SAMSUNG OTP/MTP/FLASH devices • Convenient USB connection to any IBM compatible PC or Laptop computers.
DEVELOPMENT TOOLS S3F80P5_UM_ REV1.
