Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
S3F80P5_UM_ REV1.00 CONTROL REGISTERS
Table 4-1. Mapped Registers (Continued)
Register Name Mnemonic Decimal Hex R/W
Counter A Control Register CACON 243 F3H R/W
Counter A Data Register (High Byte) CADATAH 244 F4H R/W
Counter A Data Register (Low Byte) CADATAL 245 F5H R/W
Timer 1 Counter Register (High Byte) T1CNTH 246 F6H
R
(NOTE)
Timer 1 Counter Register (Low Byte) T1CNTL 247 F7H
R
(NOTE)
Timer 1 Data Register (High Byte) T1DATAH 248 F8H R/W
Timer 1 Data Register (Low Byte) T1DATAL 249 F9H R/W
Timer 1 Control Register T1CON 250 FAH R/W
STOP Control Register STOPCON 251 FBH W
Location FCH is not mapped.
Basic Timer Counter BTCNT 253 FDH
R
(NOTE)
External Memory Timing Register EMT 254 FEH R/W
Interrupt Priority Register IPR 255 FFH R/W
NOTE: You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.
4-3