Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
RESET S3F80P5_UM_ REV1.00
SUMMARY TABLE OF BACK-UP MODE, STOP MODE, AND RESET STATUS
For more understanding, please see the below description Table 8-6.
Table 8-6. Summary of Each Mode
Item/Mode Back-up Reset Status Stop
Approach
Condition
• VDD is lower than V
LVD
• The rising edge at VDD is
detected by LVD circuit.
(When VDD ≥ V
LVD
)
• Watch-dog timer overflow
signal is activated.
• STOPCON ← # A5H
STOP
( LD STOPCON,#0A5H )
( STOP)
Port status • All I/O port is floating status
• All the ports become input
mode but is blocked.
• Disable all pull-up resister
• All I/O port is floating status
• Disable all pull-up resisters
• All the ports keep the previous
status.
• Output port data is not
changed.
Control
Register
• All control register and
system register are
initialized as list of Table 8-2.
• All control register and system
register are initialized as list of
Table 8-2.
–
Releasing
Condition
• The rising edge of LVD
circuit is generated.
• After passing an oscillation
warm-up time
• External interrupt or reset
• SED & R Circuit.
Others • There is no current
consumption in chip.
• There can be input leakage
current in chip.
• It depends on control
program
8-20