Datasheet

AVR32416
3
32105-AVR32-07/08
Name Description Type
PWR
LCD panel Power enable control signal
Output
GP[7:0]
LCD General purpose lines
Output
LCDD[23:0] LCD Data Bus output Output
2.1.1 Standard configurations
The Controller supports the following interface configurations:
4-bit single scan STN display
4 parallel data lines are used to shift data to successive single horizontal lines one at
a time until the entire frame has been shifted and transferred. The 4 LSB pins of LCD
Data Bus (LCDD [3:0]) can be directly connected to the LCD driver; the upper 20 bits
of the bus (LCDD [23:4]) are not used.
8-bit single scan STN display
8 parallel data lines are used to shift data to successive single horizontal lines one at
a time until the entire frame has been shifted and transferred. The 8 LSB pins of LCD
Data Bus (LCDD [7:0]) can be directly connected to the LCD driver; the upper pins of
the bus(LCDD [23:8]) are not used.
8-bit Dual Scan STN display
Two sets of 4 parallel data lines are used to shift data to successive upper and lower
panel horizontal lines one at a time until the entire frame has been shifted and
transferred. The bus LCDD[3:0] is connected to the upper panel data lines and the
bus LCDD[7:4] is connected to the lower panel data lines. The rest of the LCD Data
Bus lines (LCDD[23:8]) are not used.
16-bit Dual Scan STN display
Two sets of 8 parallel data lines are used to shift data to successive upper and lower
panel horizontal lines one at a time until the entire frame has been shifted and
transferred. The bus LCDD[7:0] is connected to the upper panel data lines and the
bus LCDD[15:8] is connected to the lower panel data lines. The rest of the LCD Data
Bus lines (LCDD[23:16]) are not used.
TFT single scan display (24-bit resolution)
Up to 24 parallel data lines are used to shift data to successive horizontal lines one at
a time until the entire frame has been shifted and transferred. The 24 data lines are
divided in three bytes that define the color shade of each color component of each
pixel. The LCDD bus is split as LCDD[23:16] for the blue component, LCDD[15:8] for
the green component and LCDD[7:0] for the red component. If the LCD Module has
lower color resolution (fewer bits per color component), only the most significant bits
of each component are used.
TFT single scan display (16-bit resolution)
Up to 16 data lines are used to shift the pixel data at each pixel clock cycle. Each
color gets six data lines of which 5-bits are color information and 1-bit the intensity.
The LCDD bus is split as LCDD[23:18] for the blue component, LCDD[15:10] for the
green component and LCDD[7:2] for the red component.
The Table 2-2 summarizes the above configurations and signal multiplexing.