Datasheet

AVR32416
17
32105-AVR32-07/08
LCD controller driver configures the prescaler unit according the configuration it gets from the
board setup code or later on from the fbset tool. As previously mentioned can a scaler only
divide the clock by 2^n (n=0…). If an exact pixel clock is needed the “lcdc_clk” must be a
multiple of 2 or exactly the desired clock rate.
A good solution is to use the PLL1 as input for the “lcdc_clk” because it provides the ability to
get very close to desired clock rate. To switch the “lcdc_clk” to PLL1 following function calls
have to be edited by replacing “pll0” with “pll1” (in file
arch/avr32/mach-
at32ap/at32ap700x.c)
:
clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
Next step is to actually configure the PLL1 to get the desired clock rate. Following
functions can be used to set up the PLL1 (available since kernel version 2.6.25; for
earlier versions the user has to set up the PLL1 manually).
static int pll1_set_parent(struct clk *clk, struct clk *parent)
static long pll1_set_rate(struct clk *clk, unsigned long rate,
int apply)
static void pll1_mode(struct clk *clk, int enabled)
3.6.2.4 DMA optimizations
If the LCD Controller has to transfer a lot of data from or to the external memory some
optimizations may be needed to avoid a buffer-underrun resulting in de-
synchronization of the timing generator. To get the maximum available bandwidth
also the HSB bus matrix should run at the maximum possible frequency. Keep in
mind that the CPU must always at the same or higher rate of the HSB bus.
LCD controller as fixed master
A High Speed Bus Matrix slave can only be connected to one master at a time. After
the master has finished, the slave device has three possibilities that can be
configured:
• If no other master request is pending, the slave disconnects the master.
• If no other master request is pending, the slave stays connected to the current
master.
• If no other master request is pending, the slave connects to the fixed master that
has been specified in the configuration.
The DMA Controller of the LCD Controller can be set as a fixed master for the
external bus interface. This means after another master has accessed the external
bus interface it sets the bus back to the LCD Controller. So no switching has to be
done when new data has to be fetched from a frame buffer in the external memory.
This results in a faster access time. To set up the LCD Controller as default master of
the external bus interface the fields DEFMSTR_TYPE and FIXED_DEFMSTR have to
be set up in the SCFG4 register. Please take a look at chapter “HSB Bus Matrix” and
chapter “Memories” of the device datasheet for a detailed description.
Priority-Based Arbitration
The slave, here the external bus interface, uses a round robin algorithm by default to
schedule accesses of masters to its self. This can be critical if other masters request
access to the slave and thus reducing the bandwidth for the LCD Controller. This can
lead to a buffer underflow in the LCD Controller, resulting in loss of synchronization. A
typical symptom of a buffer underflow is when the image on the screen is shifted
vertically/horizontally. To resynchronize the timing generator and thus getting back a