Datasheet

16
AVR32416
32105-AVR32-07/08
GCCTRL6 = 0
GCCTRL7 = 16
osc32k users= 1 on 32768 Hz
osc0 users=24 on 20000000 Hz
pll0 users=23 on 140000000 Hz
cpu users=22 on 140000000 Hz
hsb users=20 on 70000000 Hz
pba users=10 on 35000000 Hz
pclk users= 1 on 35000000 Hz, for pdc.0
mck users= 1 on 35000000 Hz, for pio.0
mck users= 1 on 35000000 Hz, for pio.1
mck users= 1 on 35000000 Hz, for pio.2
mck users= 1 on 35000000 Hz, for pio.3
mck users= 1 on 35000000 Hz, for pio.4
usart users= 1 on 35000000 Hz, for atmel_usart.0
usart users= 1 on 35000000 Hz, for atmel_usart.2
spi_clk users= 1 on 35000000 Hz, for atmel_spi.0
twi_pclk users= 0 off 35000000 Hz, for atmel_twi.0
pclk users= 1 on 35000000 Hz, for ssc.0
pbb users= 6 on 70000000 Hz
pclk users= 1 on 70000000 Hz, for at32_pm.0
pclk users= 1 on 70000000 Hz, for intc.0
hmatrix_clk users= 1 on 70000000 Hz
pclk users= 1 on 70000000 Hz, for smc.0
pclk users= 1 on 70000000 Hz, for systc.0
pclk users= 1 on 70000000 Hz, for macb.0
mci_clk users= 1 on 70000000 Hz, for atmel_mci.0
pclk users= 0 off 70000000 Hz, for atmel_usba_udc.0
pclk users= 0 off 70000000 Hz
pclk users= 0 off 70000000 Hz, for abdac.0
ebi users= 1 on 70000000 Hz
hramc users= 1 on 70000000 Hz
mck users= 1 on 70000000 Hz, for smc.0
hclk users= 1 on 70000000 Hz, for pdc.0
hclk users= 1 on 70000000 Hz, for dmaca.0
hclk users= 1 on 70000000 Hz, for macb.0
hck1 users= 1 on 70000000 Hz, for atmel_lcdfb.0
hclk users= 0 off 70000000 Hz, for atmel_usba_udc.0
pico users= 1 on 140000000 Hz
lcdc_clk * users= 1 on 70000000 Hz, for atmel_lcdfb.0
gclk0 * users= 1 on 11666666 Hz
pll1 users= 0 off 0 Hz
sample_clk * users= 0 off 20000000 Hz, for abdac.0
gclk1 * users= 0 off 20000000 Hz
gclk2 * users= 0 off 20000000 Hz
gclk3 * users= 0 off 20000000 Hz
gclk4 * users= 0 off 20000000 Hz
osc1 users= 0 off 12000000 Hz
The first part of the output shows the content of registers that are relevant for the configuration
of the clock system. The register content is described in the device datasheet. The rest of the
output is the clock tree. An asterisk (*) means that this clock may be tied to another parent
clock. For example a generic clock (gclk0, gclk1 …) can be tied to osc0, osc1, pll0 and pll1.
The user count shows how many active sub clock nets are tied to this parent. The on/off value
shows if the clock is active or not. The last two values describe the frequency at which the
clock runs and which driver module uses the clock.
Setting up an exact pixel clock
For the LCD controller setup is especially the “lcdc_clk” in the clock tree of interest. This clock
is fed into the LCD controller and will end up as pixel clock output after a prescaler unit. The