Datasheet

12
AVR32416
Figure 3-2 Display timings
All timings in the gray area represent the blanking area. For the internal
synchronization mechanism, the display may need some dummy data at the
beginning and/or end of a line, and at the beginning and/or end of a frame. This is
called blanking. The dummy pixels/lines are not part of the frame buffer are therefore
managed by the LCD Controller. Some delays must be introduced in vertical and
horizontal timings to support it. These delays are often described as
vertical/horizontal front/back porch delays in the display datasheets.
The maximum and minimum timing supported by the LCD Controller are listed in
Table 3-5. Thus if the display should be supported it should not exceed these timing
parameters. Especially if monitor that need VESA timings is connected via a video
DAC these maximum and minimum ratings are relevant due to the short maximum
pulse sync length.
Table 3-5. Maximum and minimum LCD controller timing parameters
Parameter Min Max Unit
Vertical Front Porch (lower_margin) 1 256 Lines
Vertical Back Porch (upper_margin) 1 256 Lines
Horizontal Front Porch (right_margin) 1 2048 Pixel Clock Cycles
Horizontal Back Porch (left_margin) 1 256 Pixel Clock Cycles
Vertical Pulse Width (vsync_len) 1 64 Lines
Horizontal Pulse Width (hsync_len) 1 64 Pixel Clock Cycles
The next structure that is needed is fb_monspecs and it contains as the name implies
the specification of the display. The definition can be found in the header file
include/linux/fb.h with information to all structure members. At least following fields
should be filled out according to the monitor specification:
static struct fb_monspecs __initdata atstk1000_default_monspecs = {
.manufacturer = "SNG",
32105-AVR32-07/08