Datasheet

AVR32416
11
32105-AVR32-07/08
.right_margin = 33,
.upper_margin = 10,
.lower_margin = 10,
.hsync_len = 16,
.vsync_len = 1,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
},
};
The fields must be filled out according to the datasheet of the LCD. The pixel clock
must be in picoseconds, the horizontal timings in number of pixel clocks and the
vertical timings in number of scanlines.
Table 3-4. Video mode configuration structure members
Parameter Description
name Name of the frame buffer video mode
refresh Refresh rate of the display
xres Horizontal display size in pixels (active/visible pixels)
yres Vertical display size in pixels
pixelclock
Desired pixel clock rate in pico seconds. Use the macro
KHZ2PICOS() to convert from kHz to pico seconds. The pixel
clock can be calculated from:
Pixel clock in Hz = (xres + left_margin + right_margin +
hsync_len) x (yres + upper_margin + lower_margin +
vsync_len) x refresh
left_margin, right_margin
Horizontal blanking in number of pixel clocks (refer to
picture…). The minimum is 1 although 0 will be accepted too
(both will lead to a register value of 0)
upper_margin, lower_margin Vertical blanking in scanlines
hsync_len
Horizontal sync pulse width in pixel clock cycles. The minimum
is 1 although 0 will be accepted too (both will lead to a register
value of 0)
vsync_len
Vertical sync pulse width in pixel clock cycles. The minimum is
1 although 0 will be accepted too (both will lead to a register
value of 0)
sync
Sync pulse polarity. Set FB_SYNC_HOR_HIGH_ACT if
horizontal sync pulse is active high. Set
FB_SYNC_VERT_HIGH_ACT if vertical sync pulse is active
high.
vmode
Only non-interlaced is supported. Set this to
FB_VMODE_NONINTERLACED
The Figure 3-2 summarizes all relevant timings.