Datasheet

- 28 -
datasheet SD Card
Rev. 1.0
MMBTFxxGWBCA-xMExx
5.5.7 Bus Timing (High-speed Mode)
Figure 5-15. Timing Diagram data Input/Output Refrenced to Clock (High-Speed)
[Table 5-7] : Bus Timing - Parameter Values (High-Speed)
NOTE:
1) In order to satisfy severe timing, host shall drive only one card.
Parameter Symbol Min Max. Unit Remark
Clock CLK ( All values are referred to min. (V
IH
) and max. (V
IL
)
Clock frequency Data Transfer Mode
f
PP
050MHz
C
CARD
<= 10 pF (1 card)
Clock low time
t
WL
7ns
C
CARD
<= 10 pF (1 card)
Clock high time
t
WH
7ns
C
CARD
<= 10 pF (1 card)
Clock rise time
t
TLH
3ns
C
CARD
<= 10 pF (1 card)
Clock fall time
t
THL
3ns
C
CARD
<= 10 pF (1 card)
Inputs CMD, DAT (referenced to CLK)
Input set-up time
t
ISU
6ns
C
CARD
<= 10 pF (1 card)
Input hold time
t
IH
2ns
C
CARD
<= 10 pF (1 card)
Outputs CMD, DAT (referenced to CLK)
Output delay time during Data Transfer Mode
t
ODLY
14 ns
C
L
<= 40 pF (1 card)
Output Hold time
t
OH
2.5 ns
C
L
<= 15 pF (1 card)
Total Systme capacitance for each line
1)
C
L
40 pF 1 card
50%V
DD
Clock
Input
Output
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
f
PP
t
WL
t
WH
t
THL
t
TLH
t
ISU
t
IH
t
ODLY
t
OH
Shaded areas are not valid