Datasheet
- 25 -
datasheet SD Card
Rev. 1.0
MMBTFxxGWBCA-xMExx
5.5.4 Bus Operating Conditions for 3.3V Signaling
SPI Mode bus operating conditions are identical to SD Card mode bus operating conditions.
5.5.4.1 Threshold Level for High Voltage Range
[Table 5-4] : Threshold Level for High Voltage
5.5.4.2 Bus Signal Line Load
The total capacitance of the SD Memory Card bus is the sum of the bus host capacitance CHOST, the bus capacitance CBUS itself and the capacitance
C
CARD of each card connected to this line:
Total bus capacitance = CHOST + CBUS + N * CCARD
Where N is the number of connected cards.
[Table 5-5] : Bus Operating Conditions - Signal Line’s Load
Note that the total capacitance of CMD and DAT lines will be consist of CHOST, CBUS and one CCARD only because they are connected separately to the SD
Memory Card host.
Host should consider total bus capacitance for each signal as the sum of CHOST, CBUS, and CCARD, these parameters are defined by per signal. The host
can determine C
HOST and CBUS so that total bus capacitance is less than the card estimated capacitance load (CL=40 pF). The SD Memory Card guaran-
tees its bus timing when total bus capacitance is less than maximum value of CL (40 pF). To limit inrush current caused by host insertion, card maximum
capacitance between VDD - VSS is defined as 5uF. To support host hot insertion, the host should consider decoupling capacitor connected to power line.
As SD/microSD card Cc is 5uF(Max.), 45uF(min.) is recommended for Decoupling capacitor. For more details, please refer to Appendix E of the SDA
Physical Layer Specification 3.00.
Parameter Symbol Min Max. Unit Remark
Supply Voltage
V
DD
2.7
3.6 V
Output High Voltage
V
OH
0.75*V
DD
V
I
OH
= -2mA V
DD
min
Output Low Voltage
V
OL
0.125*V
DD
V
I
OL
= 2mA V
DD
min
Input High Voltage
V
IH
0.625*V
DD
V
DD
+0.3
V
Input Low Voltage
V
IL
Vss-0.3
0.25 *V
DD
V
Power Up Time
=
250 ms
From 0V to V
DD
min
Parameter Symbol Min Max. Unit Remark
Pull-up resistance
R
CMD
R
DAT
10 100 KOhm to prevent bus floating
Total bus capacitance for each signal line
C
L
40 pF
1 card
CHOST+CBUS shall
not exceed 30 pF
Capacitance of the card for each siginal pin
C
CARD
10 pF -
Maximum signal line inductance 16 nH
f
PP
<= 20 MHz
Pull-up resistance inside card (pin1)
R
DAT3
10 90 KOhm May be used for card detection
Capacity Connected to Power Line C
C 5 uF To Prevent inrush current