Programming instructions

C1* C2* C88*
Horizontal
Sync.signal
(Hsync)
Clock signal
(CK)
Data signal
(R0～R5,G0～G5,
B0～B5)
THc
D1 D2 D3
Tds Tdh
Tch Tcl
Tc
D799
D800
Horizontal invalid data period
Horizontal invalid data period
Data
Enable signal
(ENAB)
THp
Number of clock
Number of H-data line
THe
Tes
THd
Tep
TH
DH1 DH2 DH3 DH599 DH600
Vertical invalid data period Vertical invalid data period
Vertical
Sync. signal
(Vsync)
Horizontal
Sync. signal
(Hsync)
TVh
TVp
TV
TVs
TVd
Number of V-data line
1 line
23 line
Fig.2 Input signal waveforms
Data signal
(R0～R5,G0～G5,
B0～B5)
T
Th
LD-14304 -8
*
Only when enable terminal is fixed
“
LOW
”
05-Oct-2005