Specifications

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4.15.4. Level Interrupt
As the default is Edge interrupt, set Interrupt setup register to Level. Interrupt
mode register BIT[1] is set to 1 and the mode is set to Level interrupt mode.
For Level interrupt, the interrupt pin is deactivated by reading Command status
register. When Interrupt is generated, Command status register should be read.
Figure 4-36. Level 1 Interrupt Pin Status
4.15.5. Status Register
a) Status Register Clear
Status register is automatically cleared when reading Status register after
Interrupt had been generated. But this is not automatic even if reading
Status register when 0x91 Bit[5] is set to ‘1’. In this case, write 0x00 in Status
register to clear by force.
b) Status Register Read
When Command Status Interrupt is generated, read the register to check
the type of interrupt. Each Bit of Command register shows the completion
or the status of operations according to the type of each interrupt. Read this
register, and Mode Bit is cleared. If this interrupt is generated and
command status register is not read, several Bits can be set to ‘1’. Especially,
for Level interrupt, interrupt pin is not activated and the next interrupt
cannot be used if Command Status register is not read.