Specifications

90 Issue Date: 2004/11/05 │ CONFIDENTIAL
CL765 │ Camera Application Processor
Datasheet │ Doc. #: CLQP-DS-743
b) Interrupt related to Flow Control and etc.
The status register of Flow Control and etc. is 0xe8. Read status to check the
type of interrupt when Interrupt is generated.
REG 0xe8 Description
Bit[0] Threshold condition
Bit[1] Overflow margin condition
Bit[2] Underflow margin condition
Bit[3] Overflow condition
Bit[4] Underflow condition
Bit[5] DMA operation complete condition
BIT[6] USB operation complete condition
BIT[7] SD CARD operation complete condition
BIT[8] NAND Flash ready/busy condition
BIT[9] NAND Flash ECC fail condition
BIT[10] NAND Flash operation fail condition
Table 4-27. Interrupt Status Register 0xe8
4.15.3. Edge Interrupt
When Interrupt mode register BIT[1] is 0, it is Edge interrupt. The status is Default
Interrupt of the CL765 and this interrupt is generated when Interrupt PIN is
switched from ‘High’ to ‘Low’.
When Edge Interrupt had been High, if the status is switched to Low, the status is
changed to High again after the specified time. The number of clocks of Low is
adjustable in use of Interrupt mode setup register BIT[5:2]. 4-Clock is the default.
Figure 4-35. Edge Interrupt Pin Status