Specifications

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- Bit[2] : The register to decide whether to write or read data in the sensor.
The initial value is Write mode and the default is ‘0’. If a sensor
requests a special read algorithm, it can be unavailable to read. For
more details, contact CORE LOGIC staffs.
- Bit[7] : Mode to support IIC Interface of Samsung CMOS VGA
Sensor(S5x433CA). As this sensor requires low-speed IIC routine
below 10K, the sensor runs at low speed when this bit is set. For
more details, refer to Samsung Sensor IIC Interface.
h) Vsync Shape Register (0x2b)
- Bit[0]: Sets “0” when using the sensor of which C_Data is Valid at the
High section of Vsync. If C_Data in Low section of Vsync is Valid,
uses “1”.
- Bit[1]: Sets ʺ0” when using Vsync signal of the sensor as Frame Valid
signal for the CL765. If this is set to ‘1’, the CL765 generates a new
Frame Valid signal. At this time, if there is no margin between Line
Valid signal and Frame Valid signal, the CL765 refers to the value
of Register 0x9a, adds Shape Delay to shift, and generates a new
Frame Valid signal internally.