Specifications

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The pins used in the interconnection are:
T_PCLK: 27MHz clock generated by the CL765
T_DA[7:0]: the YCbCr data output bus. The format of image data is 4:2:2-
YCbCr and the luminance(Y) and chrominance(Cb and Cr) are multiplexed
on the bus.
T_VSYNC: Vertical sync signal. The polarity is programmable (by default,
active-low).
T_HSYNC: Horizontal sync signal. The polarity is programmable (by
default, active-low).
The CCIR601/656 interface covers for various TV standard digital interfaces like
NTSC, PAL and SECAM. Table 4-25 summarizes the specification of digital
interface for each TV standard.
Standard Resolution
Resolution
(including
bank )
Frame/
Field rate
Interlaced Data format
NTSC / PAL M 720 x 480 858 x 525 30Hz/60Hz O 4:2:2-YCbCr
PAL 720 x 565 864 x 625 25Hz/50Hz O 4:2:2-YCbCr
SECAM 720 x 565 864 x 625 25Hz/50Hz O 4:2:2-YCbCr
Table 4-22. Digital Interface Specification for TV Standards
There is one configuration register (TVIF_CONFIG_REG) for the CCIR601/656
interface. It defines the interface mode, i.e., NTSC or PAL/SECAM, polarity of
sync signals, width of sync pulses and the sequence of YCbCr data output. Figure
4-29 shows timing diagram for each interface mode. In the figure vertical and
horizontal sync signals are only activated for CCIR601 interface.
D15 D14 D13 D12 D11 D10 D9 D8
BIT W/R
D7 D6 D5 D4 D3 D2 D1 D0
Function Default
TVIF_CONFIG (0x100)
EN STD
CCIR
0 VSPW[3:0] [3]
BIT W/R
HSPW[2:0] 0 0 CI HSI VSI
RGB-
Type
LCD
configur
ation
0x0
EN : CCIR656/601 interface controller enable
STD : TV standard. (0 – NTSC, 1 – PAL/SECAM)
CCIR : CCIR mode. (0 – CCIR656, 1 – CCIR601)
VSPW[3:0] : vertical sync pulse width
HSPW[3:0] : horizontal sync pulse width
CI : pixel clock polarity inversion
HIS : horizontal sync polarity inversion (default active low)
VSI : vertical sync polarity inversion (default active low)