Specifications

78 Issue Date: 2004/11/05 │ CONFIDENTIAL
CL765 │ Camera Application Processor
Datasheet │ Doc. #: CLQP-DS-743
VSPW VBFP DHEIGHT VBBP
pxl
0
pxl
1
px1
2
pxl
n
0
0
HSPW HBFP DWIDTH HBBP
VLHD
VSYNC
HSYNC
VDEN
HSYNC
CLK
VDEN
PDATA
[17:0]
0
0
CLK
PDATA
[17:12]
18bit
mode
666
mode
VSYNC
HSYNC
CLK
Figure 4-26. The Video Signal Timing Diagram for RGB-Type LCD Module
4.13.4. TV Encoder Interface
For external TV encoder, the CL765 provides CCIR601/656 interface with 8-bit
data bus, sync signals and 27MHz clock output. In CCIR601 interface mode,
horizontal/vertical-sync signals are separately provided, while for CCIR656
interface the sync information is encoded and multiplexed with YUV data output.
Figure 4-28 shows the generic interconnection between the CL765 and
TV(NTSC/PAL/SECAM) encoder.
T_OCLK
T_VSYNC
T_HSYNC
CL765
NTSC/PAL
Encoder
T_DA[7:0]
Figure 4-27. The Generic Interconnection between the CL765 and TV Encoder