Specifications
CORE LOGIC Proprietary and Confidential
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RGBIF_HSPW (0x206)
0 0 0 0 0 0 0 [8]
BIT W/R
HSPW[7:0]
Horizont
al sync
pulse
width
0x0
RGBIF_HBFP (0x207)
0 0 0 0 0 0 0 [8]
BIT W/R
HBFP[7:0]
Horizont
al blank
front
porch
0x0
RGBIF_HBBP (0x208)
0 0 0 0 0 0 0 [8]
BIT W/R
HBBP[7:0]
Horizont
al blank
back
porch
0x0
RGBIF_VLHD (0x209)
0 0 0 0 0 0 0 [8]
BIT W/R
V:HD[7:0]
Delay
from
vertical
sync to
start of
horizonta
l sync
0x0
CKI : pixel clock polarity inversion
HIS : horizontal sync polarity inversion (default active low)
VSI : vertical sync polarity inversion (default active low)
VDI : video data enable polarity inversion (default active low)
EIF[1:0] : external data bus interface mode. (00 - 18-Bit interface, 10 – 666
interface)










