Specifications

76 Issue Date: 2004/11/05 │ CONFIDENTIAL
CL765 │ Camera Application Processor
Datasheet │ Doc. #: CLQP-DS-743
R_VDEN: Video blank signal. The polarity is programmable (by default,
active-low).
IIC_SCL: IIC bus clock from the CL765 to LCD module
IIC_SDA: IIC bi-directional data signal
The CL765 contains the timing generator for RGB-Type LCD. The timing
generator generates sync signals and video blanks signal. Host CPU can program
the vide signal timing only by setting the related registers.
Additional to video timing generation, the CL765 provides two data interface
modes, 18-bit mode and 666 mode. REG_0x200 defines the data interface mode. In
18-bit mode, whole 18-bit data bus is used and a pixel is transferred to the LCD in
a pixel clock, while in 666 mode, only lower 6 bits of data bus is used and a pixel
is transferred to the LCD for 3 clock cycles. Figure 4-27 shows the general video
signal timing diagram.
D15 D14 D13 D12 D11 D10 D9 D8
BIT W/R
D7 D6 D5 D4 D3 D2 D1 D0
Function Default
RGBIF_CONFIG (0x200)
0 0 0 0 0 0 0 CKI
BIT W/R
HSI VSI VDI 0 0 0 EIFMODE
RGB-
Type
LCD
configura
tion
0x0
RGBIF_DWIDTH (0x201)
0 0 0 0 0 0 0 [8]
BIT W/R
DWIDTH[7:0]
LCD
display
width
0x0
RGBIF_DHEIGHT (0x202)
0 0 0 0 0 0 0 [8]
BIT W/R
DHEIGHT[7:0]
LCD
display
height
0x0
RGBIF_VSPW (0x203)
0 0 0 0 0 0 0 [8]
BIT W/R
VSPW[7:0]
Vertical
sync
pulse
width
0x0
RGBIF_VBFP (0x204)
0 0 0 0 0 0 0 [8]
BIT W/R
VBFP[7:0]
Vertical
blank
front
porch
0x0
RGBIF_VBBP (0x205)
0 0 0 0 0 0 0 [8]
BIT W/R
VBBP[7:0]
Vertical
blank
back
porch
0x0