Specifications
38 Issue Date: 2004/11/05 │ CONFIDENTIAL
CL765 │ Camera Application Processor
Datasheet
│ Doc. #: CLQP-DS-743
4.3.2. Clock Output Control
The CL765 provides conceptually two clock control schemes: global clock turning-
off and local clock turning-off. Global clock turning-off disables X-TAL pad and
PLL, while local clock turning-off disables only the related clock dividers.
4.3.2.1. Global Clock Turning-off (Sleep Mode)
The global clock turning-off means that all internal hardware clocks are turned off
and the chip is in sleep mode. To turn off all clocks, X-TAL pad and PLL unit has
to be disabled. This can be done by setting MHOLD register, REG_0xa1. After the
CL765 is in sleep mode, the chip can wake up by clearing the MHOLD signal or
by any activation on USB1.1 port, i.e., during the chip is in sleep mode, plugging-
in the USB port to USB host machine make the chip to wake up.
D15 D14 D13 D12 D11 D10 D9 D8
BIT W/R
D7 D6 D5 D4 D3 D2 D1 D0
Function Default
MHOLD (0xa1)
0 0 0 0 0 0 0 0
BIT W/R
0 0 0 0 0 0 0 hold
HOLD
the chip
(sleep
mode)
Default
4.3.2.2. Local Clock Turning-off
Each system clock can be turned off for power reduction when it is not used. Host
CPU can control each clock by programming the clock enable register, REG_0xdc.
D15 D14 D13 D12 D11 D10 D9 D8
BIT W/R
D7 D6 D5 D4 D3 D2 D1 D0
Function Default
Clock control (0xdc)
0 0 1 M1R M2R UR RR TR
BIT W/R
0 0 0 M1C M2C UC RC TC
System
clock
and
reset
control
Default
Each field of the register is as follow:
M1C : M1CLK output control. When it is set, M1CLK is active.
M2C : M2CLK output control. When it is set, M2CLK is active.
UC : USBCLK output control. When it is set, USBCLK is active.
RC : RGBCLK output control. When it is set, RGBCLK is active.
TC : TVCLK output control. When it is set, TVCLK is active.
M1R : software reset for hardware using M1CLK. Active low.
M2R : software reset for hardware using M2CLK. Active low.
UR : software reset for USB block. Active low.
RR : software reset for RGB-Type LCD controller. Active low.
TR : software reset for CCIR601/656 interface controller. Active low.
Bit[13] : It must be set to 1.