Specifications

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4.3.1.4. SDCLK
The frequency of SDCLK can be programmed using the following SdClkCtl_H
and SdClkCtl_L registers. The IN field must be expressed by 1’s complement. The
period of SDCLK is determined by the following equation.
Period
SDCLK
= (IM+(~IN)+1) * Period
system
For example, if you set the IN to 0x1 and set the IN to 0xff, then the period of
SDCLK is twice than that of system. The ID field is used to adjust the duty of
SDCLK. It means the count of active high cycle. In case of the above, if you set the
ID to 0x01, the result shows that the period of SDCLK is 2 system cycle and its
duty is the same.
D15 D14 D13 D12 D11 D10 D9
D8
BIT W/R
D7 D6 D5 D4 D3 D2 D1
D0
Function Default
SdClkCtl_H(0x402)
0 0 0 0 0 0 0
0
BIT W/R
0 0 0 0
IM[3:0]
IM 0x0000
SdClkCtl_L (0x400)
IN[7:0]
BIT W/R
ID[7:0]
IN/ID 0x0000