Specifications

36 Issue Date: 2004/11/05 │ CONFIDENTIAL
CL765 │ Camera Application Processor
Datasheet │ Doc. #: CLQP-DS-743
4.3.1.3. M1CLK/M2CLK/USBCLK/RGBCLK/TVCLK
The frequency of M1CLK and M2CLK is always the same and programmed by
setting the register, REG_0xdc, while the frequency of USBCLK, RGBCLK, TVCLK
are programmable by setting the registers, REG_0xdd, REG_0xde, REG_0xdf,
respectively.
D15 D14 D13 D12 D11 D10 D9 D8
BIT W/R
D7 D6 D5 D4 D3 D2 D1 D0
Function
Default
Main clock configure (0xdc)
CLK_PERIOD[7:0]
BIT W/R
CLK_LOW_PERIOD[7:0]
M1CLK/
M2CLK
divider
0x0502
USB clock configure (0xdd)
CLK_PERIOD[7:0]
BIT W/R
CLK_LOW_PERIOD[7:0]
USBCLK
divider
0x0301
RGB clock configure (0xde)
CLK_PERIOD[7:0]
BIT W/R
CLK_LOW_PERIOD[7:0]
RGBCLK
divider
0x0d06
TV clock configure (0xdf)
CLK_PERIOD[7:0]
BIT W/R
CLK_LOW_PERIOD[7:0]
TVCLK
divider
0x0603
The CLK_PERIOD field of the registers defines the total period of each clock (the
number of cycles of PLLCLK), while CLK_LOW_PERIOD filed defines the period
of signal low. Figure 4-7 shows the system clock (M1CLK as an example)
generation from PLLCLK.
(CLK_LOW_PERIOD+1) x PLLCLK
(CLK_PERIOD+1) x PLLCLK
PLLCLK
M1CLK
Figure 4-7. System Clock Generation from PLLCLK