Specifications

CORE LOGIC Proprietary and Confidential
35
www.corelogic.co.kr │
4.3.1. Frequency of System Clocks
The frequency of each system clock is programmable by setting related registers.
As described previous sections, PLLCLK is the source clock for each clock divider,
so the clock frequency of PLLCLK has to be determined before setting the counter
value of each clock divider. Each clock divider has a register that has two fields,
clock period and clock high period.
4.3.1.1. X-TAL Input Clock (XINCLK)
The X-TAL input clock (actually, clock from oscillator is acceptable) is used for
input clock for PLL hardware.
4.3.1.2. PLLCLK
The frequency of PLLCLK can be programmed by setting registers.
D15 D14 D13 D12 D11 D10 D9 D8
BIT W/R
D7 D6 D5 D4 D3 D2 D1 D0
Function
Default
PLL frequency divider (0x50)
0 PLL_N[6:0]
BIT W/R
PLL_M[7:0]
PLL
divider
value
0x0
PLL post divider (0x51)
0 0 0 0 0 0 0 0
BIT W/R
0 0 0 0 0 0 0 OD
PLL post
divider
0x0
The frequency of PLLCLK is determined by following equation:
F
PLLCLK = (PLL_M / PLL_N) x (1 / 2
PLL_OD
) x FXINCLK
There are constraints for above equation:
1MHz < (FXINCLK / PLL_N) < 15MHz
100MHz < (FPLLCLK x (1 / 2
PLL_OD
)) < 500MHz