Specifications

34 Issue Date: 2004/11/05 │ CONFIDENTIAL
CL765 │ Camera Application Processor
Datasheet │ Doc. #: CLQP-DS-743
4.3. CLOCK UNIT
The CL765 has on-chip PLL of which output clock (PLLCLK) frequency is up to
200MHz. The Clock Unit uses the PLL output clock as its source clock and has
various system clock dividers. The system clocks used for internal hardware
blocks are as follows;
M1CLK and M2CLK: system main clocks. The M1CLK is used for Host
interface and internal memories, while M2CLK is used for JPEG codec, scaler,
image effecter, etc. By providing separated two main clocks, Host CPU can
turn off non-operating hardware blocks and reduce power consumption. The
frequency of the clocks is 32MHz (recommended).
USBCLK: clock for USB1.1 controller. The frequency for the clock must be
48MHz.
RGBCLK: clock for RGB-Type LCD controller. Host CPU can program the
clock frequency with respect to LCD size.
TVCLK: clock for CCIR601/656 interface unit. The frequency for the clock
must be 27MHz.
SDCLK: clock for SD card controller. The clock is used for line clock of SD
card interface. The frequency of the clock is programmable ranging from
1MHz to 10MHz.
As shown in Figure 4-6, due to single source clock (PLLCLK) for clock dividers,
USBCLK and TVCLK can not be generated at the same time – They need the fixed
clock frequencies, 48MHz for USBCLK and 27MHz for TVCLK, and 432MHz for
input clock is required to generate them by using integer dividers. Therefore, the
CCIR601/656 controller and USB controller can not be activated at the same time.
In addition to generating system clocks, clock unit provides turning-off features
for each system clock for the purpose of reducing power consumption.
X_TAL
X_TAL
PLLCLK
MCLK
Divider
USBCLK
Divider
RGBCLK
Divider
RGBCLK_CE
USBCLK_CE
M2CLK_CE
M1CLK_CE
M1CLK
SDCLK
Divider
SDCLK
M2CLK
USBCLK
RGBCLK
TVCLK
TVCLK_CE
TVCLK
Divider
PLL
Figure 4-6. Block Diagram of Clock Unit