Specifications

CORE LOGIC Proprietary and Confidential
17
www.corelogic.co.kr │
2. FEATURES
2.1. HOST INTERFACE
16bit 80-Type Parallel Host interface
Indirect Addressing: Uses 2-bit Address bus.
8/16/18 bit Parallel LCD bypass mode supported
2.2. MEMORY
Embedded 256K bytes of SRAM
FIFO for flow-control, Video Buffer, OSD Buffer, BMP Buffer, Thumbnail
Buffer and Strip Buffer Embedded
2.3. LCD SUPPORT
Supports LCD bypass mode
supports 80-Type and RGB-Type LCD modules
Supports 4 gray, 16 gray, 8/12/16/18 bit Color STN/UFB/TFT LCD modules
Includes Video Buffer for high speed GRAM write
Supports high resolution LCD modules (up to 176 x 220)
Supports programmable Display Window Size
Supports Sub-LCD at the same features as Main LCD
2.4. SENSOR SUPPORT
CCIR601, CCIR656, YCbCr 4:2:2 Compliant with 8-bit Interface
Internal Clock Divider 1/1, 1/2, 1/4 for Sensor Clock Output
Supports Standard IIC BUS
Programmable Clock Polarity
Up to 3M pixel resolution(2048 x 1560)