Specifications

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Figure 4-35. Edge Interrupt Pin Status ......................................................................90
Figure 4-36. Level 1 Interrupt Pin Status................................................................... 91
Figure 4-37. Read ID – Flowchart............................................................................. 103
Figure 4-38. Page Program – Flowchart................................................................... 104
Figure 4-39. Page Read – Flowchart......................................................................... 107
Figure 4-40. Block Erasure – Flowchart ................................................................... 109
Figure 4-41. Copy-Back – Flowchart........................................................................ 110
Figure 4-42. Host Interface Timing – Write............................................................. 112
Figure 4-43. Host Interface Timing – Read.............................................................. 112
Figure 4-44. DMA Controller Interface Timing – NAND Flash Memory Read. 113
Figure 4-45. DMA Controller Interface Timing – NAND Flash Memory Write 113
Figure 4-46. NAND Flash Memory Timing (ex. TACLS=1, TWRPH0=2,
TWRPH1=1)........................................................................................... 114
Figure 4-47. DMA Controller & SD Card I/F Block Diagram ............................... 115
Figure 4-48. FAT Table for DAM............................................................................... 116
Figure 4-49. SD Initialization Process ...................................................................... 117
Figure 4-50. SD Polling Mode Read without FAT .................................................. 118
Figure 4-51. SD DMA Mode Read without FAT..................................................... 119
Figure 4-52. SD Polling Mode Write without FAT.................................................. 120
Figure 4-53. SD DMA Mode Write without FAT .................................................... 121
Figure 4-54. SD DMA Mode Read with FAT........................................................... 122
Figure 4-55. SD DMA Mode Write with FAT ..........................................................122