Specifications

116 Issue Date: 2004/11/05 │ CONFIDENTIAL
CL765 │ Camera Application Processor
Datasheet │ Doc. #: CLQP-DS-743
4.20.2. DMA Controller
DMA controller consists of Buffer part, HQ part, and Memory controller I/F.
Buffer part receives one-block unit from NAND and SD and HQ part transmits
several blocks under the commands from CPU. When DMA transmits data to the
local memory via the memory controller, the unit of data is adjustable by setting
registers. The connection between DMA buffer and other parts is configured with
16bit interface and the structure is Little Endian. DMA controller selects data flow
to CPU, SD, and NAND I/F in use of registers. For NAND, one-cell unit access is
available. But for SD, the mode is varied into DAM mode and polling mode
depending on the access to DAM buffer part after transmitting blocks. DMA
mode of SD is varied into DMA mode to transmit DMA of a single bulk block and
Table mode to create commands of SD or NANA internally in use of a table. For
NAND, only Table mode exists. The configuration of Table is as follows.
Figure 4-48. FAT Table for DAM
Table is on the local memory and transmitted to DMA HQ part through setting
relative registers. DMA part processes the table and transmits the relative
command set to SD and NAND. Data tranceived through this process directly
access memory regardless of CPU.
4.20.3. SD I/F
SD I/F complies with SD Memory Card Specification 1.0. The types of SD memory
card are 4bit and 1bit and they allows transmission of 512byte block only. SD I/F
internally includes CRC generator to detect errors. All of external signals of SD I/F
should be pulled-up except clock signals. Also, the variable clock mode exists for
initialization.