Specifications

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4.19.9.2. DMA Controller I/F Timing
Data transfer for Local memory access is performed through DMA Controller
interface as follows.
FlRxReq
F2MDt [15:0]
Valid Data End of Valid Data
NPgDone [1]
NPgDone [0]
M2CLK
Figure 4-44. DMA Controller Interface Timing – NAND Flash Memory Read
Figure 4-45. DMA Controller Interface Timing – NAND Flash Memory Write