Specifications

CORE LOGIC Proprietary and Confidential
111
www.corelogic.co.kr │
Copy-Back – CPU Command Mode
REG Description Value
0x50 NAND flash On 0x0001
0x52
CLE(command latch enable) cycle
generation
0x0001
Program command 1st cycle
=0x00
0x54
ALE(address latch enable) cycle
generation
0x0XXX
5 address cycle repeat
Source address =0xXX
0x52
CLE(command latch enable) cycle
generation
0x006b
Program command 2nd cycle
=0x35
0x52
CLE(command latch enable) cycle
generation
0x010b
Program command 1st cycle
=0x85
0x54
ALE(address latch enable) cycle
generation
0x0XXX
5 address cycle repeat
Destination address =0xXX
0x52
CLE(command latch enable) cycle
generation
0x0021
Program command 2nd cycle
=0x10
0x52
CLE(command latch enable) cycle
generation
0x00e1 Read-status command =0x70
0x56 Read cycle generation
0x0001
Read read-status-bit
Table 4-45. Copy-Back - CPU Command Mode