Specifications

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D. Block Erasure
For Erasure operation, the registers should be set as following flow chart. Before
programming in the NAND flash memory, Erasure operation is required. When
operating Erasure, the whole block which includes the row address is erased.
Then Status read register is read to check if Erasure operation had successfully
completed.. If the result is Erasure Fail, the fail is reported in use of an interrupt or
polling. Also, under DMA command mode, the result is reported to DMA
controller, too.
Figure 4-40. Block Erasure – Flowchart
Block Erasure – CPU Command Mode
REG Description Value
0x50 NAND flash On 0x0001
0x52
CLE(command latch enable) cycle
generation
0x00c1
Program command 1st cycle
=0x60
0x54
ALE(address latch enable) cycle
generation
0x0XXX
3 row address cycle repeat
Program address =0xXX
0x52
CLE(command latch enable) cycle
generation
0x01a1
Program command 2nd cycle
=0xd0
0x52
CLE(command latch enable) cycle
generation
0x00e1 Read-status command =0x70
0x56 Read cycle generation 0x0001 Read read-status-bit
Table 4-43. Block Erasure – CPU Command Mode