Specifications

108 Issue Date: 2004/11/05 │ CONFIDENTIAL
CL765 │ Camera Application Processor
Datasheet │ Doc. #: CLQP-DS-743
Page Read – CPU Command Mode
REG Description Value
0x50 NAND flash On 0x0001
0x52
CLE(command latch enable) cycle
generation
0x0001 Program command 1st cycle =0x00
0x54
ALE(address latch enable) cycle
generation
0x0XXX
5 address cycle repeat
Program address =0xXX
0x52
CLE(command latch enable) cycle
generation
0x0061 Program command 2nd cycle =0x30
0x56 Read cycle generation 0x0001 Number of page(512) repeat
0x52
CLE(command latch enable) cycle
generation
0x0121
Program command 1st cycle in spare
data =0x05
0x54
ALE(address latch enable) cycle
generation
0x0XXX
2 column address cycle repeat
Program address =0xXX
0x52
CLE(command latch enable) cycle
generation
0x01c1
Program command 2nd cycle in spare
data =0xe0
0x56 Read cycle generation 0x0001 Number of spare(16) repeat
Table 4-41. Page Read – CPU Command Mode
Page Read – DMA Command Mode
REG Description Value
0x82
DMA HQ transfer, NAND flash
select
0x3000
FAT table definition
0x84 0xXXXX
FAT table low 16bit start address in
Local memory
0x86
FAT table start address
0x00XX
FAT table high 5bit start address in
Local memory
0xac 0xXXXX
Block data to be stored low 16bit start
address in Local memory
0xae
Block data start address
0x00XX
Block data to be stored high 5bit start
address in Local memory
0xb0 0xXXXX
Spare data to be stored low 16bit start
address in Local memory
0xb2
Spare data start address
0x00XX
Spare data to be stored high 5bit start
address in Local memory
0xb4
FAT transfer control register
setting
0x0102
FATCtl[15:8] =# of FAT number
FATCtl[ 1] = FAT Read
FATCtl[ 0] = FAT Write
Table 4-42. Page Read – DMA Command Mode