Specifications

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Page Program – CPU Command Mode
REG Description Value
0x50 NAND flash On 0x0001
0x52
CLE(command latch enable) cycle
generation
0x0121
Program command 1st cycle
=0x80
0x54
ALE(address latch enable) cycle
generation
0x0XXX
5 address cycle repeat
Program address =0xXX
0x66
Write value setting 0x00XX
Number of byte per page(512)
repeat Value
[7:0]=data_value_for_IO[7:0]
0x58
Write cycle generation 0x0001
Number of byte per page(512)
repeat
0x52
CLE(command latch enable) cycle
generation
0x0121
Program command 1st cycle in
spare data =0x85
0x54
ALE(address latch enable) cycle
generation
0x0XXX
2 column address cycle repeat
Program address =0xXX
0x66
Write value setting 0x00XX
Number of byte per spare(16)
repeat Value
[7:0]=data_value_for_IO[7:0]
0x58
Write cycle generation 0x0001
Number of byte per spare(16)
repeat
0x52
CLE(command latch enable) cycle
generation
0x0021
Program command 2nd cycle
=0x10
0x52
CLE(command latch enable) cycle
generation
0x00e1 Read-status command =0x70
0x56
Read cycle generation 0x0001 Read read-status-bit
Table 4-39. Page Program – CPU Command Mode