Specifications

102 Issue Date: 2004/11/05 │ CONFIDENTIAL
CL765 │ Camera Application Processor
Datasheet │ Doc. #: CLQP-DS-743
4.19.7. ECC (Error Correction Code)
The NANDCtrl block has Hardware ECC function that reports the errors of fail bit
which occurs when accessing the memory. ECC detection is available only under
DMA command mode and Software corrects ECC. When detecting the fail bit in
Read operation, the NANDCtrl block informs whether an error has occurred to
the DMA controller and the modem CPU by polling or generating an interrupt.
While performing Write operation, it generates ECC. If the ECC is different from
the ECC of Spare area, it inserts the generated ECC instead of the ECC of the
spare area.
The positions of ECC in Spare area are basically following 4 assignments. For
other assignments, it is available to configure Register (0x68) to support the
position of ECC and S-ECC.
512byte page, x8 cell width –ECCPosit=0x06, SECCPosit=0x09
256word page, x16 cell width –ECCPosit=0x06, SECCPosit=0x09
2Kbyte page, x8 cell width - ECCPosit=0x08, SECCPosit=0x0b
1Kword page, x16 cell width - ECCPosit=0x08, SECCPosit=0x0b
4.19.8. Flow Control
For the operations of the NAND flash memory, it is required to set registers as
shown in the following flow chart. The setting varies according to the type of the
external NAND flash memory device. Following example shows the case of 2Gbit
page size and x8 cell width by enabling spare byte Read/Write.
Prepare Register Setting before Operation – ex) 2Gbit page, x8 cell width
REG Description Value
0x5a
ALE cycle type setting & Latch cycle
and write/read enable duration
configuration
0x0051 2/4/8Gbit
0x5c
NAND flash memory size
configuration
0x6cae
X8, 2Gbit,
16byte/page spare
0x5e NAND flash controller configuration 0x0001 Enable ECC
0x68 Spare assignment configuration 0x00b8 Type 3: x8, 2Kbyte page
0x6a Interrupt mask configuration 0x0002
‘NIntr_OpFail’ enable
’NIntr_ECCFail’ enable
Table 4-37. Prepare Register Setting before Operation