Specifications

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4.19.4. Modem CPU I/F
Modem CPU interface uses 8bit width address line bus and 16bit width data line
bus. Internally, Host bus interface is not connected to NANDCtrl block directly,
but connected to the bus interface multiplexed in DMA controller, because under
DMA command mode, Mode CPU receives the commands decoded via DMA
controller. Read address[7:0]와 Read data[15:0] which have not been multiplexed
exist for Modem CPU to read the registers of NANDCtrl block directly.
4.19.5. DMA Controller I/F
The local memory is not accessed directly by NANDCtrl block, but accessed via
DMA controller. To read/program NAND flash memory, request signals are
transmitted to DMA controller and data is transferred. At this time, as the local
memory data width is 16bit, 16bit data is transmitted to DMA controller without
regard to the cell width of NAND flash memory; 8bit or 16bit.
When writing data read from NAND flash memory in the local memory,
‘FlRxReq’ request signal and ‘F2MDt[15:0]’ data are transmitted to DMA controller.
When programming data read from the local memory, receives ‘WrDtRdy’ signal,
which shows whether DMA controller internal buffer is full or not, to check if
data transfer is available. When transmitting ‘FlTxReq’ request to DMA controller,
‘M2FStb’ strobe signal and ‘M2FDt[15:0]’ data is received.
Like this, to access the local memory, DMA controller should control the access.
When under DMA command mode, page (256byte/ 512byte) Read/ Program
operation has completed, the operation completion and errors are informed in use
of ‘NPgDone’ signal.
4.19.6. NAND Flash Memory I/F
Through register configuration, NANDCtrl block provides interfaces with various
types of NAND flash memories:
Support 256 or 512 bytes/page NAND flash memory
Support 3 or 4 or 5 address cycle and sector pointer NAND flash memory
Support 8 or 16 bits memory interface bus
NAND flash memory timing by Device type is also supported through
register configuration.