Specifications

100 Issue Date: 2004/11/05 │ CONFIDENTIAL
CL765 │ Camera Application Processor
Datasheet │ Doc. #: CLQP-DS-743
4.19. NAND FLASH I/F
4.19.1. Overview
The NANDCtrl block runs the external NAND flash memory. It receives
commands from Modem CPU and works as an interface between a local memory
and the external NAND flash memory for data transfer. Actually, the NANDCtrl
block interfaces with the NAND flash and DMA controller accesses the local
memory and decodes commands. It supports various types of NAND flash
memories through the internal register configuration.
4.19.2. Features
CPU command mode: A user can read/ erasure/ program NAND flash
memory using combination of command by SW.
DMA command mode: This operation is needed Local memory access
through DMA controller. A user can page read/ page write/ erasure NAND
flash memory using only one command setting.
support 256 or 512 bytes/page NAND flash memory
support 3 or 4 or 5 address cycle NAND flash memory
support 8 or 16 bits memory interface bus
hardware ECC detecting and ECC code generating (S/W correcting)
4.19.3. Operation Scheme
NAND flash operation is classified to CPU command mode and DMA command
mode. Under CPU command mode, the NAND flash directly receives commands
required to create cycles for operation from the Modem CPU and performs
NAND flash operation. Under DMA command mode, the operations performed
frequently such as page write, page read and block erasure are performed in use
of only one command. As the local memory is accessed through DMA controller,
the command is achieved by defining FAT table and setting table address and FAT
transfer control register. It is unavailable for NANDCtrl block to perform all
operations of NAND flash memory in use of one command. Therefore, for the
operations which have not been defined in the above DMA command mode, CPU
command mode is used to combine the cycles required to operations.