Document Number: CLQP-DS-743 Data Sheet CL765 Camera Application Processor VERSION 0.
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www.corelogic.co.kr │ This document contains information of CORE LOGIC’s new product, CL765. Specifications and information herein are subject to change without notice. Use of this specification for product design requires an executed license agreement from CORE LOGIC. CORE LOGIC shall not be liable for technical or editorial errors or omissions contained herein; nor for incidental or consequential damages resulting from the furnishing, performance, or use of this material.
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www.corelogic.co.kr │ Table of Contents 1. Introduction................................................................. 11 1.1 Scope .............................................................................................................. 11 1.2. Overview....................................................................................................... 12 1.3. JPEG Encoder/Decoder............................................................................... 13 1.3.1. JPEG Encoding..........
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.1. Block Diagram ............................................................................................. 28 4.2. Host Interface ............................................................................................... 30 4.2.1. LCD Access Port ................................................................................. 31 4.2.2. Bypass Mode ............................................................................
www.corelogic.co.kr │ 4.15.3. Edge Interrupt................................................................................... 90 4.15.4. Level Interrupt .................................................................................. 91 4.15.5. Status Register................................................................................... 91 4.16. GPIO Setup .................................................................................................. 92 4.17. Image Effect.......................
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 List of Tables Table 4-1. Usage of LCD Access Port (Connecting both A0 and ADS Situation).............................................. 31 6 Table 4-2. Usage of LCD Access Port (Not Connecting A0 and ADS) ................. 31 Table 4-3. Register Read/Write .................................................................................. 33 Table 4-4. Examples of Preview Rotation ..................................................
www.corelogic.co.kr │ Table 4-35. Other Markers ........................................................................................... 98 Table 4-36. Reserved Markers ..................................................................................... 98 Table 4-37. Prepare Register Setting before Operation .......................................... 102 Table 4-38. Read ID – CPU Command Mode.......................................................... 103 Table 4-39.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 List of Figures Figure 4-1. CL765 System Block Diagram ............................................................... 28 Figure 4-2. Modem CPU Interface............................................................................ 30 Figure 4-3. Bypass Mode ........................................................................................... 32 Figure 4-4. Camera Mode: Register Write ..........................................
www.corelogic.co.kr │ Figure 4-35. Edge Interrupt Pin Status ...................................................................... 90 Figure 4-36. Level 1 Interrupt Pin Status................................................................... 91 Figure 4-37. Read ID – Flowchart ............................................................................. 103 Figure 4-38. Page Program – Flowchart................................................................... 104 Figure 4-39.
CL765 │ Camera Application Processor Datasheet │ Doc.
www.corelogic.co.kr │ 1. INTRODUCTION 1.1. SCOPE In this document, hardware functional specification for CL765 – CORE LOGIC’s Mobile Camera Application Processor – is described. The main scope of this document includes internal hardware functionality, interfaces to external devices, AC/DC characteristics, register descriptions and package information. This document is written and organized for mainly two groups of engineers: system designer and software programmer.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 1.2. OVERVIEW CORE LOGIC’s CL765 is an easy, convenient and high-performance camera application processor (CAP) designed to meet the needs of mobile platformrelated industry, manufacturers and developers: least effort and cost in developing their system, as well as a lot of outstanding features and functionalities.
www.corelogic.co.kr │ 1.3. JPEG ENCODER/DECODER The CL765 has a fully-hardwired JPEG codec. It encodes an image incoming from CMOS/CCD image sensor, and decodes a JPEG stream sent from Host CPU. During the encoding/decoding, various image processing like scaling, image effects are pre/post-processed by using dedicated hardware blocks. 1.3.1.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 1.4. EMBEDDED MEMORY The CL765 embeds 256K bytes of internal SRAM that is accessible by Host CPU (The CL765 embeds Strip Buffer also, but the Strip Buffer is not visible and accessible for Host CPU. It is internally used only). The internal memory is used mainly for JPEG encoding/decoding and buffer for OSD image. Host CPU can access the whole space of the memory through Host interface protocol (refer to 4.2).
www.corelogic.co.kr │ 1.5. OSD The CL765 supports OSD. OSD is the function to compound Camera image and Background BMP image and dispkay that on LCD. OSD has Overwrite function and Overlay function and Chroma-Key is used to perform the functions. ChromaKey is a special key used for the area where OSD BMP image and Camera image are displayed. It is used to distinguish Camera image from OSD BMP image.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 Additional to LCD interface, the CL765 provides CCIR601/656 interface for external TV encoder. The visual data output through the interface is compliant to CCIR601 or CCIR656 specification for either NTSC encoders or PAL/SECAM encoders. 1.8. CMOS/CCD IMAGE SENSOR INTERFACE The CL765 supports various CMOS/CCD image sensor interface.
www.corelogic.co.kr │ 2. FEATURES 2.1. HOST INTERFACE 16bit 80-Type Parallel Host interface Indirect Addressing: Uses 2-bit Address bus. 8/16/18 bit Parallel LCD bypass mode supported 2.2. MEMORY Embedded 256K bytes of SRAM FIFO for flow-control, Video Buffer, OSD Buffer, BMP Buffer, Thumbnail Buffer and Strip Buffer Embedded 2.3.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 2.5. DISPLAY SUPPORT Supports Frame Rate Up to 30 fps (depends on Sensor Frame rate) Supports Fully Hardwired Image Scalar (up to 4X Zoom – horizontally 2X and vertically 2X - in comparing to the original image size) Supports Real Zoom Supports Real-time Hardwired Display Rotation (90°, 180°,270°,mirror, flip) Supports OSD modes (i.e.
www.corelogic.co.kr │ 2.8.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 2.13. CLOCK AND POWER Full CMOS Technology Equipped with PLL of which output frequency is programmable Supports 5MHz to 20MHz for input clock Supports maximum 40MHz of internal main clock (32MHz is recommended) Typically consumes under 100uA during Sleep Mode Supports Preview & Capture Mode, under 28mA Consumption @ 20MHz (internal main clock) 2.14.
www.corelogic.co.kr │ 3. PIN DESCRIPTION 3.1.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor 3.2. PIN DESCRIPTION Modem CPU Interface (29 pins) Pin Pin Name I/O Type NO.
www.corelogic.co.kr │ Pin Pin Name I/O Type NO. Drive Interface (mA) Group Description Sub-LCD chip select.
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www.corelogic.co.kr │ LCD Interface (23 pins) Pin Pin Name I/O Type NO.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor Other pins (13 pins) Pin Pin Name I/O Type NO. Drive Interface (mA) Group Description Pin to control the action of Strobe A10 STROBE Output 4 K5 USB_DP Input/Output USB USB Differential Data Bus K6 USB_DM Input/Output USB USB Differential Data Bus light. - GPIO When not using these pins, connect them to GND.
www.corelogic.co.kr │ Pin Pin Name I/O Type NO. Drive Interface (mA) Group Description - GPIO When not using these pins, A9 GPIO_5 (SD_D3) Input/Output 4 GPIO / SD CARD connect them to GND. - SD CARD Interface Assigned to SD CARD Data 3. Power pins (19 pins) Pin Pin Name I/O Type NO.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4. FUNCTIONAL DESCRIPTIONS 4.1. BLOCK DIAGRAM Figure 4-1 shows the overall system diagram of the CL765. CL765 Video Out MODEM CPU SENSOR Figure 4-1. CL765 System Block Diagram The basic function of each hardware block in the figure is as follow: Frame Buffer: Temporary buffer for video that the CL765 manages.
www.corelogic.co.kr │ Strip Buffer: Transforms the line data received from sensor into block data, or JPEG-decoded block data into line data. Memory Controller: Controls various accesses to Frame buffer. JPEG Codec: JPEG encoder/decoder System Controller: Controls power and the CL765 overall actions. YCbCr-to-RGB Converter: Transforms YCbCr into RGB, or vice versa. LCD/OSD Controller: Controls main-LCD and sub-LCD. CPU Type LCD Interface: Controls and Interface CPU type main-LCD and sub-LCD.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.2. HOST INTERFACE Figure 4-2 shows the generic interconnection between the host (modem CPU) and the CL765. The interface used for mainly two types of interactions, register read/write and LCD access. For register read/write, the interface is called “Index/Data Port”, while for LCD access, the interface is called “LCD Access Port”. M_RESET_N Figure 4-2.
www.corelogic.co.kr │ 4.2.1. LCD Access Port LCD Access Port bypasses 1) the CL765’s any bypass mode and 2) LCD lock status in camera mode for Data (16 bits) and control signals (CS, WR, RD). LCD access port has Port 0 and Port 1. Port 0: When using A0 and ADS connections together, it bypasses write of LCD command and command parameters for most vendors LCD. Port 1: When using A0 and ADS connections together, it writes LCD GRAM data.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.2.2. Bypass Mode When the CL765 is not Camera Mode, the CL765 bypasses the Data selectively according to the gating of M_CS_N (MS_CS_N) from M_SD. The example of waveform is as below. Figure 4-3.
www.corelogic.co.kr │ 4.2.3. Register Read_n/Write_n Port The CL765 accesses registers by indirect addressing method. There are two types for this purpose, Index and Data. Index Port: Selects Read/Write register. Data Port: Reads/writes data to the selected register from Index Port. Port M_SA M_CS_N M_RD_N M_WR_N 2 0 1 0 2 0 0 1 3 0 1 0 3 0 0 1 Index port Data port Operation Selects Register Read from currently selected register.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor 4.3. CLOCK UNIT The CL765 has on-chip PLL of which output clock (PLLCLK) frequency is up to 200MHz. The Clock Unit uses the PLL output clock as its source clock and has various system clock dividers. The system clocks used for internal hardware blocks are as follows; M1CLK and M2CLK: system main clocks. The M1CLK is used for Host interface and internal memories, while M2CLK is used for JPEG codec, scaler, image effecter, etc.
www.corelogic.co.kr │ 4.3.1. Frequency of System Clocks The frequency of each system clock is programmable by setting related registers. As described previous sections, PLLCLK is the source clock for each clock divider, so the clock frequency of PLLCLK has to be determined before setting the counter value of each clock divider. Each clock divider has a register that has two fields, clock period and clock high period. 4.3.1.1.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor 4.3.1.3. M1CLK/M2CLK/USBCLK/RGBCLK/TVCLK The frequency of M1CLK and M2CLK is always the same and programmed by setting the register, REG_0xdc, while the frequency of USBCLK, RGBCLK, TVCLK are programmable by setting the registers, REG_0xdd, REG_0xde, REG_0xdf, respectively.
www.corelogic.co.kr │ 4.3.1.4. SDCLK The frequency of SDCLK can be programmed using the following SdClkCtl_H and SdClkCtl_L registers. The IN field must be expressed by 1’s complement. The period of SDCLK is determined by the following equation. PeriodSDCLK = (IM+(~IN)+1) * Periodsystem For example, if you set the IN to 0x1 and set the IN to 0xff, then the period of SDCLK is twice than that of system. The ID field is used to adjust the duty of SDCLK. It means the count of active high cycle.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor 4.3.2. Clock Output Control The CL765 provides conceptually two clock control schemes: global clock turningoff and local clock turning-off. Global clock turning-off disables X-TAL pad and PLL, while local clock turning-off disables only the related clock dividers. 4.3.2.1. Global Clock Turning-off (Sleep Mode) The global clock turning-off means that all internal hardware clocks are turned off and the chip is in sleep mode.
www.corelogic.co.kr │ 4.4. OPERATION MODE REGISTER When modem CPU commands the CL765 to execute certain action, it is done through Operating mode (0x00) register, and each bit does the following. Bit[1] = Preview (When this bit is set, the CL765 displays the image on LCD for preview.) Bit[2] = Still Capture (Set this bit for still image capture, the CL765 clears this bit after still image capture is completed.) Bit[4] = Set this bit for Movie capture.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 Bit[14] = Reserved Bit[15] = Converts BMP images (YCbCr Format) stored in Memory to JPEG images. If the still image capture is set during preview action, the CL765 displays on LCD the image captured the last and stops any further updating. Then, it sends the interrupt to modem CPU to inform the completion of still image storage, and clears bits for preview and still capture.
www.corelogic.co.kr │ 4.5. PREVIEW 4.5.1. Preview Setup The CL765 displays images entered from Camera on LCD. For the image display, 3Mega Pixel (2048x1536) is supported in maximum. In Preview mode, the area to display on LCD is selected on the image entered from Camera. And the target is set as same as the Display resolution of LCD. After the above setup is completed, the CL765 converts the area selected in the original image of Camera to Preview Resolution to display on LCD in use of Video scalar. 1.
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www.corelogic.co.kr │ 4.5.2. Preview Rotation The CL765 supports rotation of Mirror, Flip, 90°, 180°, and 270° in Preview. With simple register setup, Preview rotation is available. Preview rotation only supports LCD Display and is not applied to JPEG Encoding. To use Rotation function, it is necessary to set Preview area again. The relative register is 0x01.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 0x01 Flip Horizontal Horizontal Flip Bit[4:2]: 3’b100 Vertical Flip 0x01 (mirror) Bit[4:2]: 3’b101 Flip Vertical Table 4-4. Examples of Preview Rotation 4.5.3. Preview Frame Skip Preview Frame Display interval is adjustable. Frames entered from Camera are sampled and displayed on LCD. The relative register is 0x0f.
www.corelogic.co.kr │ 4.6. JPEG ENCODING 4.6.1. Still JPEG Encoding Perform JPEG encoding by converting the image entered from Camera to the various sizes. Camera image supports up to 3 Mega-Pixel(2048x1536). JPEG Codec is JPEG Baseline method and supports Camera image of YCbCr 4:2:2 Format. The capacity of the internal SRAM buffer is limited. Therefore JPEG file should be read in use of Flow Control before the JPEG buffer which had been set while decoding is over-flown.
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www.corelogic.co.kr │ 4.6.3. MJPEG Encoding The CL765 supports MJPEG. The CL765 internally has 256 kbyte SRAM. Among the whole SRAM buffer, It is available to use the SRAM area except Video buffer area as MJEPG buffer. MJPEG buffer can use the SRAM area except Preview buffer. When only MJPEG buffer is used, MJPEG encoding time is limited by the capacity of the buffer. This limitation on encoding time is free with using Flow Control; available to encode MJPEG without any limitation on buffer capacity.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.7. JPEG DECODING The CL765 can decode JPEG file of Baseline format, the most used among JPEG formats. It is available to decode images up to VGA in maximum. Followings are the YCbCr formats supported. -. YCbCr 4:4:4 -. YCbCr 4:2:2 -. YCbCr 4:1:1 -. YCbCr 4:2:0 4.7.1. Still JPEG Decoding JPEG Decoding supports resolution up to 3 Mega-Pixel in maximum.
www.corelogic.co.kr │ 4.8. SRAM BUFFER SETUP The CL765 has internally SRAM of 256KByte and the SRAM is classified into its purpose for use. SRAM Read/Write is performed by 2btye unit. SRAM buffer areas are Video buffer area, OSD buffer area, and PIP buffer area. Each buffer area is used only when the relevant functions are used, so it is available for each buffer to share SRAM area. Following description details each buffer.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 Figure 4-9. Example of SRAM Buffer Setup 4.9. SRAM READ Describes how to read data from SRAM in the CL765. This is used to read SRAM for JPEG,MJPEG encoding and Video buffer read. This chapter describes the case that Flow Control is not used. a) SRAM address Point setup b) 0x0b setup for Index Register c) Data Port Read 4.10. SRAM WRITE Describes how to write data in SRAM in the CL765.
www.corelogic.co.kr │ 4.11. PIP (PICTURE IN PICTURE) PIP is a function that inserts a specific icon or text image in JPEG images while performing JPEG encoding. Also, like OSD, it is available to display PIP image on Preview. PIP supports 8 Color Tables and each Color Table is configured as YCbCr 4:2:2. It is available to use various colors in PIP by changing the table values. For PIP, 1 pixel consists of 4bits and 16bit data is configured with 4 pixels. Each 4bit sets PIP enable bit and PIP table.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor Color Table is set as follows. The configuration of 0xa8~0xaf is as following table. Y 6Bit [15:10] Cb 5Bit [9:5] Color Cr 5Bit [4:0] Value White 0xFE10 Blue 0x6298 Red 0x659B Green 0x9906 Yellow 0xD872 Purple 0x6298 The colors can be configured as shown in the above table. The colors are configured by referring the following formula. Y = 0.299R + 0.587G + 0.114B Cb = -0.1687R – 0.3313G + 0.5B + 128 Cr = 0.
www.corelogic.co.kr │ 4.12. FLOW CONTROL Flow Control enables to capture or playback still images or moving pictures by using a small memory efficiently. In the existing method, as data is not readable until all of the captured JPEG images are saved in the memory, it is unavailable to capture the image of which capacity exceeds the memory capacity. But with Flow Control, the host can simultaneously read data from the memory as writing captured JPEG data in the memory.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor for a while to avoid Underflow when the Underflow Margin interrupt is generated. The Overflow margin is generated when the Write speed is quicker than the Read speed and the interval between the write point and the read point is within a certain range. The host should accelerate the Read speed when Overflow margin is generated. If the Overflow occurs, the host should generate Error for the overflow.
www.corelogic.co.kr │ 4.12.2. Modem CPU Requirement Encoding/Decoding in use of Flow Control is performed in real-time. So, if the memory access time of Modem CPU is late, Overflow or Underflow can occur. Therefore, Modem CPU should quickly write or read data in the memory to prevent Overflow or Underflow. In case of Encoding, following factors can have the influence upon Flow Control: FIFO size, I/O 1 cycle time, and JPEG data size.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor 4.12.3. Flowchart & Pseudo Code Figure 4-12. Encoding Flowchart Error #1 – This error cannot occur in the normal status. If it has occurred, check if the register setup is correct. Error #2 – This error means that an overflow has occurred. It can occur when FIFO size is set too small or JPEG Quality factor (Q factor) is set too low. In this case, make the FIFO size larger or Q factor higher.
www.corelogic.co.kr │ Encoding Pseudo Code U16 Sara_FlowStillCapture(U16 *stillImg, U32 *stillsize) { Define the variables. CamStatusSetMode(); // Status Register Clear. must.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor } return 0; Figure 4-13. Decoding Flowchart Error #1 – This error cannot occur in the normal status. If it has occurred, check if the register setup is correct. Error #2 – This error means that an underflow has occurred. It can occur when FIFO size is set too small or writing speed is low. In this case, make the FIFO size larger or speed up the writing by adjusting CS timing of the external I/O.
www.corelogic.co.kr │ Decoding Pseudo Code U16 Sara_FlowStillDecode(U16 *stillImg, U32 stillsize) { Define the variables. CamStatusSetMode(); FlowSetRegSize(); // Status Register Clear. must. // Set a Flow control register CamSRAMWritePath_Still(); // Open the memory path from host to Sara //Check data size for writing if(FIFO Size >= wordSize) { Write a Data. DoCameraOperation(Sara_DO_STILL_DECODE); // Decoding Waiting for Decoding Done. return TRUE; } else Write a data as FIFO Size. // Do Decoding.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.13. DISPLAY UNIT The Display Unit of the CL765 includes alpha-blender and output device interface. The alpha-blender blends input source images – video image and OSD images – and compose one image which will be displayed on output devices, LCD’s and TV. For external visual device interface, the CL765 provides three types of external visual equipment interfaces: 80-Type LCD, RGB-Type LCD and TV encoder.
www.corelogic.co.kr │ For multiplexing of the sequence, following operation is used: if (current_position is within FG image area) { RDST = RFG GDST = GFG BDST = BFG } else { RDST = RBG GDST = GBG BDST = BBG } For alpha blending of above operation, following equation is used: RDST = RFG x α + RBG x (1 – α) GDST = GFG x α + GBG x (1 – α) BDST = BFG x α + BBG x (1 – α) Video Image Image on display device OSD Image α CORELOGIC α=0 α=0.5 α=1.0 CORELOGIC Figure 4-15.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor After alpha blending, the result image is displayed on output visual device through provided output device interfaces: 80-Type LCD interface, RGB-Type LCD interface and external TV encoder interface. The output visual device interfaces share common physical pins of the CL765, and hence only one device can be activated at a time. 4.13.1. Data Format of OSD Image The CL765 provides three types of bitmap formats for OSD.
www.corelogic.co.kr │ The alpha expansion, shown in Figure 4-18, is performed by referencing the hardwired-expansion-table. The table contents are listed in Table 4-8. For an example, When A_INDEX is 3 then result α is 4-bit 0110, i.e., 6 in integer and 0.4 (= 6/15) in fixed-point. C_INDEX[2:0] Result α[3:0] 0 0 1 2 2 4 3 6 4 8 5 10 6 12 7 15 Table Table 4-6. Alpha Expansion Table 4.13.1.2.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor 4.13.1.3. 565-RGB For 565-RGB format, R, G and B component of each pixel are constructed by bit expansion logic operation as shown in Figure 4-20. For the format alpha value of each pixel is not available. Instead, the value of REG_0x18[7:4] is used as alpha value for all pixels.
www.corelogic.co.kr │ Video Image Image on display device OSD Image CORELOGIC ? REG_0x19 CORELOGIC color = REG_0x19 (i.e., chroma-key color) Figure 4-19.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor 4.13.2. 80-Type LCD Interface The CL765 can control two LCD’s, one for main-LCD and the other for sub-LCD. Figure 4-22 shows the generic connections between the CL765 and LCD’s. L_CS_N L_ADS L_RD_N Main LCD L_WR_N L_DA[17:0] CL765 LS_CS_N Sub LCD Figure 4-20.
www.corelogic.co.kr │ VSYNC L_CS_N L_ADS L_WR_N L_DA[17:0] CMD0 CMD1 CMD2 CMDn L_DA0 L_DA1 L_DA2 L_DA3 L_DA4 L_DAn - CMD0, CMD1 .... CMDn : LCD Command - L_DA0, L_DA1 ..... L_DAn : LCD Gram Data Figure 4-21. Camera Mode and LCD_Display The CL765 sets commands for LCD display in use of two ways; the one is to set parameters in commands; and the other is to set LCD commands and parameters to display on LCD as decided sequence.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor The above figure shows the timing diagram of the level to set LCD commands and parameters in LCD Interface. According to the characteristics of the LCD, the polarity of L_ADS can be changed. However, the overall timing of LCD Command/Parameter setup is the above. The values shown in the above table are the timing of internal operation and it is no need for the host to set values for them.
www.corelogic.co.kr │ 4.13.2.1. 80-Type LCD Setup 1. LCD Setup 1 a) LCD Type 1 Setup Set register values according to the LCD color and Bus type. LCD Type 1 Description BIT[1:0] BUS type setup: 8bit, 16bit, 18bit BIT[4:2] Color Depth: 260K, 65K,4K, 256 BIT[5] RGB Order BIT[6] RGB Data align BIT[8:7] Write Low Period BIT[10:9] Write High Period Table 4-8. LCD Type 1 Setup b) LCD Type 2 Setup Set the method to send commands and data to LCD.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor d) LCD GRAM Setup After completing LCD Window setup, LCD GRAM Write is performed. GRAM start address setup can be varied by LCD Driver. Also, GRAM write command can be optional. In the CL765, it is available to set all above cases in use of Register 0x46. Window Setup Description REG 0x46 Set GRAM Start address and GRAM Write.
www.corelogic.co.kr │ d) LCD Windows/Parameter Setup Set LCD Window Command/parameter in Register 0xC0-0xCF. The cycle of each command and parameter is set in Register 0xB5[7:2] and ADS Polarity is set in Register 0xB6. e) LCD GRAM Start Address/Write Command Setup Set GRAM start address and Write Command in Register 0xD0-0xD9. The whole cycle is set in Register 0xB5[13:8] and ADS Polarity is set in Register 0xB7.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor ⅰ) LCD Type 1 LCD Type 1 BIT[1:0] BIT[4:2] BIT[5] BIT[6] Value ‘01’ Remarks = 16 bit BUS ‘100’ = 65K color ‘0’ ‘0’ = RGB Changeable according to LCD Panel. = left-align N/A for 16 bit Bus BIT[8:7] ‘00’ = 1 clock Changeable depending on the input clock. BIT[10:9] ‘00’ = 1 clock Changeable depending on the input clock. REG 0x38 0x0011 Table 4-15.
www.corelogic.co.kr │ ⅳ) 0xB6 Setup 0xB7 Value Description BIT[0] ‘0’ ADS Polarity of LCD command 0x16 BIT[1] ‘1’ Parameter ADS Polarity of LCD command 0x16 BIT[2] ‘0’ ADS Polarity of LCD command 0x17 BIT[3] ‘1’ Parameter ADS Polarity of LCD command 0x17 REG setup value 0X0A Table 4-18.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor 4.13.2.2. LCD Update under Camera Mode 1) LCD Lock The CL765 has the overall control authority of the LCD when CL765 is Camera mode, Therefore, the CL765 performs the displaying onto LCD once it receives scaled Camera Data or encoding/decoding of the compressed image. If MCU must access the LCD at this point, may use LCD LOCK function to get override authority to access the LCD from the CL765.
www.corelogic.co.kr │ 2) LCD Control Flag Preview should be stopped after LCD display of the last frame has been completed. Two cases exist to stop Preview after checking if the Camera Image display on LCD has been completed. 1) Check LCD Frame update interrupt and clear Register 0x00. 2) Use LCD control flag. Set LCD control flag, and the update of frame being displayed on LCD is completed and Preview is automatically ended. 4.13.3.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor R_VDEN: Video blank signal. The polarity is programmable (by default, active-low). IIC_SCL: IIC bus clock from the CL765 to LCD module IIC_SDA: IIC bi-directional data signal The CL765 contains the timing generator for RGB-Type LCD. The timing generator generates sync signals and video blanks signal. Host CPU can program the vide signal timing only by setting the related registers.
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Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor VSYNC CLK HSYNC VLHD VSYNC HSYNC VDEN VSPW VBFP DHEIGHT VBBP HSYNC VDEN 18bit mode 666 mode CLK PDATA [17:0] pxl 0 0 pxl 1 px1 2 pxl n 0 CLK PDATA [17:12] 0 HSPW 0 HBFP DWIDTH HBBP Figure 4-26. The Video Signal Timing Diagram for RGB-Type LCD Module 4.13.4. TV Encoder Interface For external TV encoder, the CL765 provides CCIR601/656 interface with 8-bit data bus, sync signals and 27MHz clock output.
www.corelogic.co.kr │ The pins used in the interconnection are: T_PCLK: 27MHz clock generated by the CL765 T_DA[7:0]: the YCbCr data output bus. The format of image data is 4:2:2YCbCr and the luminance(Y) and chrominance(Cb and Cr) are multiplexed on the bus. T_VSYNC: Vertical sync signal. The polarity is programmable (by default, active-low). T_HSYNC: Horizontal sync signal. The polarity is programmable (by default, active-low).
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CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.14. SENSOR INTERFACE The CL765 supports various types of Sensor interfaces. The basic type of sensor that it supports is CCIR-601/656 format with 8-bit interface. 4.14.1.1. Sensor RESET and IIC Write Time Figure 4-29. Sensor RESET and IIC Write Time Initially, sets the sensor power control register. At this point, C_PWDN pin sets to Low and C_RST activates.
www.corelogic.co.kr │ Figure 4-31.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor 4.14.1.3. Registers Related to Sensor Interface a) Device ID (0x22) Sensor Device ID is decided by CIS_Type pin. In short, if CIS_TYPE[2:0] is [000], the sensor device ID is Omnivision CMOS VGA sensor and the value is 7bit Hex value 0x21(7bit data). Like this, [001] is set to Hynix CMOS VGA(0x11), [010] is set to SONY CMOS VGA(0x1f), and [011] is set to SANYO CCD VGA(0x3C).
www.corelogic.co.kr │ When supplying C_MCLK to Sensor, it generates data in synchronization with C_PCLK’s Positive Edge. At this moment, the CL765 receives the Sample Data in CbY1Y2 order. As seen in above diagram, the CL765 receives the Data and get ready to process it in synchronization with SCLK clock domain that received from the Positive Edge of C_PCLK.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 When providing power to GPIO from the point A, 0x24 should be set at the point B to activate Sensor Interface Part. Reversely, to stop Preview of the sensor, Register 0x24 should be set to 0 and turn off the power provided to the GPIO. In this case, the leaking current may flow to the sensor during the period of red part in Figure 1-4. Therefore, 0x24 should be set since providing the power to GPIO as quick as possible.
www.corelogic.co.kr │ - Bit[2] : The register to decide whether to write or read data in the sensor. The initial value is Write mode and the default is ‘0’. If a sensor requests a special read algorithm, it can be unavailable to read. For more details, contact CORE LOGIC staffs. - Bit[7] : Mode to support IIC Interface of Samsung CMOS VGA Sensor(S5x433CA). As this sensor requires low-speed IIC routine below 10K, the sensor runs at low speed when this bit is set.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor 4.15. INTERRUPT SETUP The CL765 supports Interrupt. Interrupt means the completion of several operations such as Encoding and Decoding. Edge interrupt and Level interrupt are supported. Interrupt is classified as follows. a. Operation completion: shows the completion of operations such as JPEG, OSD, and MJPEG. b. Operation status: shows the status of operations such as JPEG Capture and Decoding. c. Interrupt related to Flow Control d.
www.corelogic.co.kr │ 4.15.2. Type of Interrupt The types of Interrupt registers are as follows; interrupts related to the CL765 such as JPEG, MJPEG, Preview, and SRAM read/write and interrupts related to Flow Control. a) Interrupt related to the functions of the CL765 Read Status Register 0x05 when Interrupt is generated. When Interrupt is generated, the relevant Bit is set to ‘1’. REG 0x05 Description Bit[0] Indicates the possibility of modem CPU taking direct control of LCD.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 b) Interrupt related to Flow Control and etc. The status register of Flow Control and etc. is 0xe8. Read status to check the type of interrupt when Interrupt is generated.
www.corelogic.co.kr │ 4.15.4. Level Interrupt As the default is Edge interrupt, set Interrupt setup register to Level. Interrupt mode register BIT[1] is set to 1 and the mode is set to Level interrupt mode. For Level interrupt, the interrupt pin is deactivated by reading Command status register. When Interrupt is generated, Command status register should be read. Figure 4-36. Level 1 Interrupt Pin Status 4.15.5.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.16. GPIO SETUP The CL765 has 6 GPIOs. Basically, GPIOs are set to INPUT and it can be changed to OUTPUT by setting the register. Each GPIO Port can be used independently. REG Description Default Decide Input/Output Mode of GPIO 0x2E Bit[5:0] ‘1’= input, ‘0’ = Output 0x3f Available to set each pin to input/output mode independently. 0x2F Bit[13:8] Read enable: enables GPIO Input Mode to read the pin value.
www.corelogic.co.kr │ 4.17. IMAGE EFFECT The CL765 can apply Color effect to the images entered from Camera, preview on LCD, and encode/decode JPEG. Following image effects are supported; Warm, Cool, Fog, Negation, Summation, AND, OR, and Grey-scale.
CL765 │ Camera Application Processor Summation ANDing ORing Antique Cool 94 Issue Date: 2004/11/05 │ CONFIDENTIAL Datasheet │ Doc.
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CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.18. DATA FORMAT The CL765 supports JPEG and Raw data formats, but the use of JPEG format is recommended to minimize the image file size. Raw data format is useful when a carrier or handset maker provides the special processing of the captured image. In this case, the image is configured in YCbCr 4:2:2 format.
www.corelogic.co.kr │ DQT (0xffdb) SOS (0xffda) DRI (0xffdd) RSTm (0xffd0 ~0xffd7) APPm (0xffe0 ~ 0xffef) COM (0xfffe) In case of DHT or DQT, both the format in which the tables can be put together and expressed in a single location of the header or the format in which it is divided into several tables and expressed in different locations of the header are supported. In case of COM, a specified length of the data that comes after the marker is ignored.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor Start of Frame markers, differential, arithmetic coding Code assignment Symbol Description X’FFCD’ SOF13 Differential sequential DCT X’FFCE’ SOF14 Differential progressive DCT X’FFCF’ SOF15 Differential lossless (sequential) Table 4-32. Start of Frame Markers, Differential, Arithmetic Coding Huffman table specification Code assignment Symbol X’FFC4’ DHT Description Define Huffman table(s) Table 4-33.
www.corelogic.co.kr │ If needed, additional markers can be used, but they are not necessary and thus do not affect decoding. During JPEG compression, the CL765 only supports 4:2:2 down-sampling format due to the hardware design requests. Since most of the sensors support CCIR601 or CCIR656 format, and output format is also 4:2:2, the CL765 uses it without variation. In case of decoding, on the other hand, there are three down-sampling formats as listed below.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.19. NAND FLASH I/F 4.19.1. Overview The NANDCtrl block runs the external NAND flash memory. It receives commands from Modem CPU and works as an interface between a local memory and the external NAND flash memory for data transfer. Actually, the NANDCtrl block interfaces with the NAND flash and DMA controller accesses the local memory and decodes commands.
www.corelogic.co.kr │ 4.19.4. Modem CPU I/F Modem CPU interface uses 8bit width address line bus and 16bit width data line bus. Internally, Host bus interface is not connected to NANDCtrl block directly, but connected to the bus interface multiplexed in DMA controller, because under DMA command mode, Mode CPU receives the commands decoded via DMA controller. Read address[7:0]와 Read data[15:0] which have not been multiplexed exist for Modem CPU to read the registers of NANDCtrl block directly. 4.19.5.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.19.7. ECC (Error Correction Code) The NANDCtrl block has Hardware ECC function that reports the errors of fail bit which occurs when accessing the memory. ECC detection is available only under DMA command mode and Software corrects ECC. When detecting the fail bit in Read operation, the NANDCtrl block informs whether an error has occurred to the DMA controller and the modem CPU by polling or generating an interrupt.
www.corelogic.co.kr │ A. Read ID using CPU Command Mode It is available to read product identification information that the device has through Read ID operation. Registers are set as shown in the following flow chart. Figure 4-37.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 B. Page Program To program 256byte or 512byte-page, the registers should be set as following flow chart. The dotted lined-boxes in the following flow chart are performed only when programming in Spare area. Then Status read register is read to check if the program operation had successfully completed. If the result is Program Fail, the fail is reported in use of an interrupt or polling.
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CL765 │ Camera Application Processor Datasheet │ Doc.
www.corelogic.co.kr │ C. Page Read To read 256byte or 512byte-page, the registers should be set as following flow chart. The ECC generated from read data is compared with the ECC of the spare area. If the result is Fail, the fail is reported in use of an interrupt or polling. Also, the result is reported to DMA controller, too. ECC verification is available only when Spare R/W is enabled under DMA command mode. Figure 4-39.
CL765 │ Camera Application Processor Datasheet │ Doc.
www.corelogic.co.kr │ D. Block Erasure For Erasure operation, the registers should be set as following flow chart. Before programming in the NAND flash memory, Erasure operation is required. When operating Erasure, the whole block which includes the row address is erased. Then Status read register is read to check if Erasure operation had successfully completed.. If the result is Erasure Fail, the fail is reported in use of an interrupt or polling.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 Block Erasure – DMA Command Mode REG Description Value REG 0x60 Address value setting 0xXXXX 1st , 2nd address setting 0x62 Address value setting 0xXXXX 3rd ,4th address setting 0x64 Address value setting 0xXXXX 0x50 NAND flash On 0x001d 5th address setting Block Erasure (NANDCmd =0x07) Table 4-44. Block Erasure – DMA Command Mode E.
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CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.19.9. I/O Timing 4.19.9.1. Host I/F Timing Write: When Phenable=1 and pwrite=1, write pdata in the register which paddr indicates. Read: When Phenable=1 and pwrite=0, read the register which paddr/phaddr indicates to pdata/pfrdata. Figure 4-42. Host Interface Timing – Write Figure 4-43.
www.corelogic.co.kr │ 4.19.9.2. DMA Controller I/F Timing Data transfer for Local memory access is performed through DMA Controller interface as follows. M2CLK FlRxReq F2MDt [15:0] Valid Data End of Valid Data NPgDone [1] NPgDone [0] Figure 4-44. DMA Controller Interface Timing – NAND Flash Memory Read Figure 4-45.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.19.9.3. NAND Flash Memory I/F Timing Figure 4-46. NAND Flash Memory Timing (ex.
www.corelogic.co.kr │ 4.20. DMA CONTROLLER & SD CARD I/F 4.20.1. Block Diagram Figure 4-47.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.20.2. DMA Controller DMA controller consists of Buffer part, HQ part, and Memory controller I/F. Buffer part receives one-block unit from NAND and SD and HQ part transmits several blocks under the commands from CPU. When DMA transmits data to the local memory via the memory controller, the unit of data is adjustable by setting registers.
www.corelogic.co.kr │ 4.20.4. SD Operations 4.20.4.1. SD Initialize It is required to initialize SD card state for SD operation. The state of SD is roughly varied into Identification mode and Data transfer mode. It is absolutely required to disconnect the power of SD card when the SD card has become Inactive state. Transfer of each state is as following figure. Data transfer of SD card starts from “tran” state under Data transfer mode.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.20.4.2. SD Core Read from Card, No FAT Table Pre-read Polling Mode 1) 2) 3) 4) 5) 6) 7) Set TrNum_L(20h). (C) Set DmEn(15) and DmBkNum(1:0) of DmaCtl(82h). (C) Set SdArg_L and SdArg_H(08h, 0Ah). (C) Set SdCmHit(15), SdCmd(5:0) and RspR(14:12) of SdCtl_L(04h). (C) When SD I/F checks SdCmHit, SdCmSm block transmits a command. (S) SD I/F waits for a relative response after transmitting the command.
www.corelogic.co.kr │ DMA Mode 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) 16) Same with Polling 1). Set transfer address of TrAddr_H and TrAddr_L(86h, 84h) in DMA. (C) Same with Polling 2). Same with Polling 3). Same with Polling 4). Same with Polling 5). Same with Polling 6). Same with Polling 7). Same with Polling 8). Same with Polling 9). Same with Polling 10). Same with Polling 11). When 256*16bit buffer is full, DMA requests the memory controller.
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.20.4.3. SD Core Write to Card, No FAT Table Pre-read Polling Mode 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) Set TrNum_L(20h). (C) Set DmEn(?) and DmBkNum(?) of DmaCtl(80h). (C) Set SdArg_L and SdArg_H(08h, 0Ah). (C) Set SdCmHit(15), SdCmd(5:0) and RspR(14:12) of SdCtl_L(04h). (C) When SD I/F checks SdCmHit, SdCmSm block transmits a command.(S) SD I/F waits for a relative response after transmitting the command.
www.corelogic.co.kr │ DMA Mode 1) Same with Polling 1). 2) Set Addr_H(4:0) and Addr_L(15:0) of TrAddr_L and TrAddr_H(?) in DMA. (C) 3) Fill the contents to be transmitted to SD card in Transfer address area. (C) 4) Same with Polling 2). 5) Same with Polling 3). 6) Same with Polling 4). 7) Same with Polling 5). 8) Same with Polling 6). 9) Same with Polling 7). 10) Same with Polling 8). 11) Same with Polling 9). 12) Same with Polling 10).
CL765 │ Camera Application Processor Datasheet │ Doc. #: CLQP-DS-743 4.20.4.4. SD Core Read Using FAT 1) 2) 3) 4) 5) Make Table in the local memory.(C) Set Addr_H(4:0) and Addr_L(15:0) of TrAddr_L and TrAddr_H(?) in Table address in DMA. (C) Set the position where data is transmitted on BlkAddr_L and BlkAddr_H in DMA. (C) Set FAT control and DMA control of DMA. (C) Waits for the final interrupt from the inside of DMA. (C) Figure 4-54. SD DMA Mode Read with FAT 4.20.4.5.
www.corelogic.co.kr │ 5. ELECTRICAL CHARACTERISTICS 5.1.
Datasheet │ Doc. #: CLQP-DS-743 CL765 │ Camera Application Processor 5.2. AC CHARACTERISTICS 5.2.1. Absolute Maximum Ratings (VSS=0V) Parameter Symbol Rating Units Supply Voltage VDD V DC Input Voltage Vin V DC Input Current Iin mA Operation Temperature TOPR C Storage Temperature Tstg C 5.2.2. Recommended Operating Condition Parameter Symbol Min Typ Max Units IO Voltage Vddi V Core Voltage Vddc V Oscillation Freq. Fosc MHz 5.2.3.
www.corelogic.co.kr │ 6. PACKAGE REFERENCE The package is 100-CABGA and 8 x 8 SCSP, with 256K bytes SRAM embedded in the camera IC. Raw Ball Size Ball Pitch (A) Ball Height (B) Ball Diameter (C) 0.4mm 0.75mm 0.34mm+/-0.05 0.42mm+/-0.
