Specifications

Arcadia Motherboard Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
5-6 Freescale Semiconductor
5.4.2 Serial RapidIO
Table 5-3 describes the pinout of the high-speed port connector, when the parallel RapidIO protocol is in
use. This pinout is as defined by the RapidIO Trade Association TWG document, RapidIO Hardware
Interoperability Platform (HIP) Specification.
5.4.3 PCI Express
Table 5-4 describes the pinout of the high-speed port connector when the PCI Express protocol is used.
NOTE
This is not a standard currently supported on HIP platforms and careful
interoperability setup is required.
Table 5-3. Arcadia Serial RapidIO Connector Definition
Pin Definition Pin Definition Pin Definition Pin Definition
A1, B1 R1D1, R1D1 C1, D1 R3D1, R3D1 E1, F1 G1, H1
A2, B2 C2, D2 E2, F2 G2, H2
A3, B3 C3, D3 E3, F3 G3, H3
A4, B4 C4, D4 E4, F4 G4, H4
A5, B5 C5, D5 E5, F5 T4D1, T4D1 G5, H5 T2D1, T2D1
A6, B6 R2D1, R2D1 C6, D6 R4D1, R4D1 E6, F6 G6, H6
A7, B7 C7, D7 E7, F7 G7, H7
A8, B8 C8, D8 E8, F8 G8, H8
A9, B9 C9, D9 E9, F9 G9, H9
A10, B10 C10, D10 E10, F10 T3D1, T3D1 G10, H10 T1D1, T1D1
Notes:
1. BG(1:10), DG(1:10), FG(1:10), and HG(1:10) are all connected to system ground.
2. Blank cells are no connect.
Table 5-4. Arcadia PCIExpress Connector Definition
Pin Definition Pin Definition Pin Definition Pin Definition
A1, B1 rx0 (p,n) C1, D1 rx8 (p,n) E1, F1 G1, H1
A2, B2 rx1 (p,n) C2, D2 rx9 (p,n) E2, F2 tx15 (n,p) G2, H2 tx7 (n,p)
A3, B3 rx2 (p,n) C3, D3 rx10 (p,n) E3, F3 tx14 (n,p) G3, H3 tx6 (n,p)
A4, B4 rx3 (p,n) C4, D4 rx11 (p,n) E4, F4 tx13 (n,p) G4, H4 tx5 (n,p)
A5, B5 CLK125, n/a C5, D5 E5, F5 tx12 (n,p) G5, H5 tx4 (n,p)
A6, B6 rx4 (p,n) C6, D6 rx12 (p,n) E6, F6 G6, H6
A7, B7 rx5 (p,n) C7, D7 rx13 (p,n) E7, F7 tx11 (n,p) G7, H7 tx3 (n,p)