Specifications

MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor ix
Figures
Figure
Number Title
Page
Number
Figures
1-1 Carrier Block Diagram (Configuration 1)............................................................................... 1-4
1-2 Carrier Block Diagram (Configuration 2)............................................................................... 1-5
1-3 Daughtercard Block Diagram ................................................................................................. 1-5
2-1 Inserting Memory Module ......................................................................................................2-2
2-2 Removing Chassis Thumb Screws ......................................................................................... 2-2
2-3 Removing Chassis Top Cover................................................................................................. 2-2
2-4 Removing Chassis Side Panel................................................................................................. 2-3
2-5 Removing PCI Slot Bracket Screws ....................................................................................... 2-3
2-6 Install Carrier Card into PCI Slot............................................................................................ 2-4
2-7 Guide Pin Alignment .............................................................................................................. 2-4
2-8 Install PCI Bracket Screws ..................................................................................................... 2-5
3-1 Carrier Block Diagram (Configuration 1)............................................................................... 3-2
3-2 Carrier Block Diagram (Configuration 2)............................................................................... 3-3
3-3 Version Register (CM_VER) .................................................................................................. 3-5
3-4 Reset Control Register (CM_CSR)......................................................................................... 3-6
3-5 Reset Control Register (CM_RST)......................................................................................... 3-6
3-6 Reset Control Register (CM_LED)......................................................................................... 3-7
3-7 PCI Control/Status Register (CM_PCI).................................................................................. 3-7
3-8 Reset Control Register (CM_DMA)....................................................................................... 3-8
3-9 CE/CPM Architecture............................................................................................................. 3-9
3-10 CDS ATM Architecture ........................................................................................................3-12
3-11 CDS Ethernet Architecture (Configuration 1) ...................................................................... 3-14
3-12 CDS Ethernet Architecture (Configuration 2) ...................................................................... 3-14
3-13 CDS Local Bus Architecture................................................................................................. 3-16
3-14 CDS Clock Architecture ....................................................................................................... 3-19
3-15 CDS PCI Architecture........................................................................................................... 3-20
3-16 CDS Exception Architecture................................................................................................. 3-21
3-17 CDS Carrier Reset Architecture............................................................................................ 3-23
3-18 CDS Carrier I2C Architecture............................................................................................... 3-25
3-19 CDS Configuration Logic .....................................................................................................3-27
3-20 CDS Power Architecture....................................................................................................... 3-28
4-1 Daughtercard Placement ......................................................................................................... 4-2
4-2 CDC with 783 BGA Processor Example ................................................................................ 4-3
4-3 Daughtercard Block Diagram ................................................................................................. 4-4
4-4 CDS Memory Architecture ..................................................................................................... 4-5
4-5 CDC Memory Termination ..................................................................................................... 4-7
4-6 CDS Local Bus Architecture...................................................................................................4-9
4-7 CDS Dual-PCI Architecture.................................................................................................. 4-13