Specifications

CDS Daughtercard Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor 4-17
The power budget must be compared to approximately 170 W available to the carrier, and to the portion
of that power required for the carrier itself.
4.14.1 Processor Core Power
Core power (V
DD
) to the processor is supplied using a switching regulator. It is capable of supplying core
voltages in the range 0.925–2.0 V in 25-mV steps over the lower range (0.925 to 1.275 V), and 5-mV steps
elsewhere. Up to 15 A (14–30 W) is available, though most processors use much less than that. The core
power is trimmed using the standard switch +I2C override method, or using the low-power VRM encoding
standards as shown in Table 4-10.
The processor core power flows through a Maxim (MAX4372FEUK) current-measuring device. This
analog measurement circuit outputs a voltage corresponding to the current demand of the processor,
measured across a low-ohm resistor. The analog signal is conditioned and measured with an I2C-based
+12 V 2 × 0.45 A 0.9 A 10.8 W
Total 137.5 W
Table 4-10. CDC VDD (Vcore) Encoding Table
VID
Output Voltage
VID
Output Voltage
43210 43210
11111 OFF
1
01111 OFF
1
11110 0.925 V 01110 1.300 V
11101 0.950 V 01101 1.350 V
11100 0.975 V 01100 1.400V
11011 1.000 V 01011 1.450 V
11010 1.025 V 01010 1.500 V
11001 1.050 V 01001 1.550 V
11000 1.075 V 01000 1.600 V
10111 1.100 V 00111 1.650 V
10110 1.125 V 00110 1.700 V
10101 1.150 V 00101 1.750 V
10100 1.175 V 00100 1.800 V
10011 1.200 V 00011 1.850 V
10010 1.225 V 00010 1.900 V
10001 1.250 V 00001 1.950 V
10000 1.275 V 00000 2.000 V
Note:
1. The 1.250- and 0.900-V options may be selected by configuring the MAX1813 to 50-mV step mode (remove resistor R___)
and setting the code to 01010 or 10011, respectively. Refer to the MAX1813 datasheet for other codes when in this mode.
Table 4-9. CDC Available Power
Power Pins × Current Current Power