Specifications

CDS Daughtercard Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
4-12 Freescale Semiconductor
Note: The FCI connector supports 0.45 A/pin.
4.7 Carrier Pinouts
For a detailed pinout, including numbering, refer to Appendix B.1, “Carrier/DaughterCard Connectors
Pinout.”
4.8 Clock
There are five pre-defined clock sources available to the CDC, as detailed in Table 4-5.
As discussed in Section 3.8, “Clock,” clocks may or may not be synchronous to any other clock. Also, they
may or may not be synchronous to the de-assertion timing of HRESET
. Such an environment is determined
by the carrier board.
Power +12V VCC_12V 2 0 Imax = 0.9 A, Pmax = 10.8 W
Power –12V VCC_12N 0 1 Imax = 0.5 A, Pmax = 5.4 W
Ground GND 95 86
USB 2.0 U1_TP, U1_TN, U1_OC
U2_TP, U2_TN, U2_OC
6
Subtotal 387 344
Spares 13 56 Bring up to next connector size
Tot a l 40 0 40 0
Table 4-5. CDC Clocks
Clock Signal Interface Rate Notes
PCICLK LVTTL 33–66 MHz Generally supplied by either the PCI clock of the HIP motherboard, or the
local clock of the carrier. Used by processors/bridge logic which operate
synchronous to the PCI interface.
PCICLK2 LVTTL 66 MHz Created by the CDC for cards with secondary PCI slots. An on-board
oscillator is provided to generate this clock (which is independent of all
other clocks).
SYSCLK LVTTL 0–300 MHz Supplied by the HIP motherboard, independent of the PCICLK rate. Used
by processors/bridge logic which operate asynchronous to the PCI
interface.
RTCCLK 512 MB 16 MHz Timebase clock
GTXCLK 1 GB 125 MHz Clock for GBit Ethernet PHYs and/or interfaces.
Table 4-4. CDS Daughtercard Connector Overview (continued)
Signal Group Signals
Left Pin
Count
Right Pin
Count
Notes