Specifications

CDS Daughtercard Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor 4-9
interface properly with the peripherals supported on the carrier. If differing access sizes are needed,
LB_SIZ can be generated dynamically, however, it is typically only set to one particular size.
NOTE
The data bus size option only affects how the CDC and carrier provide
access to Flash memory (particularly for boot code). It does not affect the
ability to generate cycles of any size to other devices; in particular, to the
uTCOM/TCOM devices and/or anything else attached to the CPM
interface.
Figure 4-6 shows the local bus implementation for the CDC. See Table 3-16 for a description of the local
bus interface signals.
Figure 4-6. CDS Local Bus Architecture
Processor
LAD[0:31]
LA[27:31]
LBCTL
LALE
SDRAM
Latch
DeMux
A
Buf
Q
B
LE
DIR
D
Y
DQ[31:0]
A[15:0]
LCS[0:7]
LB_A[27:31]
LB_D[0:31]
LB_DP[0:7]
Buf
LB_A[0:26]
Constant
A10, WE,
RAS, CAS
LB_OE, LB_WE
LB_CS
LBCLK
LB_CLK
CLK
LGPL
LB_GPL
LBSYNC
LB_LALE
LMA[0:31]
Buf
LB Connector
LB_LBCTL
LB_SZ[0:1]
Buf
Delay
LDP[0:7]
CS
LCS2