Specifications

CDS Daughtercard Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor 4-7
4.4.1 DDR Interface Termination
The termination of the DDR interface is critically important because of its ability to operate at high speeds.
The general architecture of the termination is shown in Figure 4-5.
Figure 4-5. CDC Memory Termination
Unlike most series termination usage, for DDR control signals, the 22-Ω termination resistors (1%) are
placed near the DDR DIMM. This facilitates routing breakout, which improves the signal integrity of data.
This improvement matches the loaded impedance of unidirectional signals on the DIMM (address,
command, chip-select).
I2C_SCK SPD I2C SCK SCL 92
N/A SPD write protect WP 90
<var> SPD address SA[0:2] 181, 182, 183 2
GVDD Memory IO power V
DDQ
15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136,
143, 156, 164, 172, 180
GVDD Memory power V
DD
7, 38, 46, 70, 85, 108, 120,148
GND Ground GND 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93,
100, 116, 124, 132, 139, 145, 152, 160, 176
NC V
DDID
82
SPD EEPROM power V
DDSPD
184
Notes:
1. MA14 unused with current JEDEC DDR modules. MA14 is brought out to a termination resistor in the event a standard MA14
is defined for DDR SDRAM modules.
2. Address = 3B001 for DIMMs #1.
3. Clock (0:2) for DIMM #1 only. The remaining clock outputs are terminated to ground through a capacitor.
Table 4-1. CDS DDR SDRAM Properties (continued)
DDR SDRAM
Signal
Description JEDEC DDR SDRAM Module Pin Notes
Processor
Control
27 Ω
V
TT
DIMM
22 Ω
27 Ω
Signal
Data
Signal
27 pF
22W
22 Ω
Optional
0.1 μF
0.1 μF
0.1 μF