Specifications

CDS Daughtercard Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor 4-5
Figure 4-4. CDS Memory Architecture
The memory subsystem bus is single-endedly terminated via series and parallel terminations. Power for
the termination plane (V
TT
) is supplied through a National LP2995, which supplies up to 1.5 A
continuously (3 A transient response). This is sufficient for the upper limit generally expected for DDR
termination, while actual termination power requirements are significantly less.
In addition, the LP2995 supplies V
REF
to the processor and DIMMs. The V
REF
/V
TT
levels are adjustable
using a resistor to alter the threshold slightly. By default, V
REF
is set to 1.25 V.
As shown in Figure 4-4, the DDR SDRAM parity/ECC pins (MECC[7:0]) are used to display debugging
information in certain debug modes. In such a case, the MECC pins must be disconnected from the
memory interface (since CB[7:0] from the DDR memories are bidirectional) and routed to the debugging
interface connector.
The processor supplies two differential clocks to the memory modules. These signals are not parallel
terminated. The signals are described in Table 4-1.
Processor DDR DIMM
MRAS RAS
CAS
WE
CKE[1:0]
A[14:0]
DQ[63:0]
DQS[0:8]
DM[8:0]
CB[7:0]
MCAS
MWE
MCKE[1:0]
MCS
[1:0]
MCS
[2:3]
MA[14:0]
MBA[1:0]
MDQS[8:0]
MDM[8:0]
MDQ[63:0]
MCK[0:1]
MCK
[0:1]
MSYNC_OUT
MVREF
MEM_RST
I2C_SDA
I2C_SCK
S[1:0]
BA[1:0]
MCK[2:3]
MSYNC_IN
MCK
[2:3]
MECC[7:0]
CK[0:1]
CK
[0:1]
RESET
SDA
SCL
V
REF
V
term
Resistors and Decoupling
LP2995
V
TT
V
REF’
R
term
R
term
R
term
R
term
V
DDQ
MDEBUG
QS
Header
MDBG
S[3:2]