Specifications

CDS Carrier Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
3-30 Freescale Semiconductor
Table 3-27. CDS Local Bus ‘STAT’ Header Definition
Pin Signal Mictor Definition
3 LBCLK2 Even clock
4 LBCTL Even D15 (MSB)
5WE3
/BS3 Even D14
6WE2
/BS2 Even D13
7WE1
/BS1 Even D12
8WE0
/BS0 Even D11
9 CDC_SPR1 Even D10
10 CDC_SPR2 Even D9
11 Even D8
12 Even D7
13 Even D6
14 GPL5 Even D5
15 GPL4 Even D4
16 GPL3 Even D3
17 GPL2 Even D2
18 GPL1 Even D1
19 GPL0 Even D0 (LSB)
36 LALE Odd clock
35 Odd D15 (MSB)
34 RD
Odd D14
33 WR
Odd D13
32 DP3 Odd D12
31 DP2 Odd D11
30 DP1 Odd D10
29 DP0 Odd D9
28 Odd D8
27 CS7
Odd D7
26 CS6
Odd D6
25 CS5
Odd D5
24 CS4
Odd D4
23 CS3
Odd D3
22 CS2
Odd D2
21 CS1
Odd D1
20 CS0
Odd D0 (LSB)