Specifications

CDS Carrier Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
3-26 Freescale Semiconductor
3.13 Configuration
The CDS contains many configuration options to allow it to adapt to the user's application. Many of these
options are static: set at startup and remain unchanged. Others are asserted during the reset sequence
(generally, this occurs on the processor/system bridge, that is, on the CDC) and after reset is concluded,
revert to some other function.
Table 3-24. CDS I2C Bus Properties
I2C Device I2C Device I2C Address Data Size Notes
CDC system ID EEPROM AT24C64A 0x56 (1010_110x) 8192
Remote control/configuration port PCA9557 0x1C (0011_100x)
0x1D (0011_101x)
0x1E (0011_110x)
0x1F (0011_111x)
81, 2
Notes:
1. CDC daughtercards may also have configuration switches, at addresses 0x18.01B.
2. These devices are at different addresses and have different programming sequences as compared to
the Elysium use of dual PCF9555s.
Table 3-25. CDS Configuration Parameters
Configuration Option Config. Signal
Control
Method
I2C Config Port
Switch Default
Dev Bits
ATM1 mux disable ATM1_SEL Switch or I2C 0x24 0 SW3(8) 1 = CPM->ATM1
ATM2 mux disable ATM2_SEL Switch or I2C 1 SW3(7) 1 = CPM->ATM2
FE mux disable FE_SEL Switch or I2C 2 SW3(6) 1 = CPM->FE
ADTech select ADT_SEL Switch or I2C 3 SW3(5) 0 = AdTech NOT active
ATM1 width ATM1_16BIT
Switch or I2C 4 SW3(4) 1 = ATM1 16-bit IO
ATM2 enable ATM2_EN
Switch or I2C 5 SW3(3) 1 = ATM2 enabled
Uart_Sel Switch or I2C 6 SW3(2) 1 = Uart_Sel
Reserved Switch or I2C 7 SW3(1) 1 = Reserved
User-defined USERMODE(0:1) Switch or I2C 0x25 1–0 SW2(8:7) 00 = User defined
Reserved Switch or I2C 2 SW2(6) 1 = Reserved
1
Reserved Switch or I2C 3 SW2(5) 1 = Reserved
Event select EVE_SEL Switch or I2C 4 SW2(4) 1 = EVE = SRESET
NVRAM disable NVRAM_DIS Switch or I2C 5 SW2(3) 1 = NVRAM available
Flash boot select ROMMODE(0:1) Switch or I2C 7–6 SW2(2:1) 00 = Standard Flash
Local clock V(6:1) select LCLK_V(6:1) Switch or I2C 0x26 5–0 SW4(3:8) 001000 = Part of 33MHz
SYSCLK
Local clock R(2:1) select LCLK_R(2:1) Switch or I2C 7–6 SW4(1:2) 10 = Part of 33MHz
SYSCLK